Macro Placement Guideline in ASIC Physical Design

In all Previous blogs, Floorplan terminology and requirement before starting floorplan is explained. in this article, Lets  discuss the macro placement guideline. Macro placement satisfying the set of rules will ease the physical design and reduced the challenges at subsequent stages of Physical Design flow. Generally Macros are bigger in size, which cause critical design issues leading to increase wire net delay , cross-talk , IR drop. Hence these guidelines are help to save lots of time in future stages of flow.

This is 5th topics from "Mastering Floorplan" series. If you are reading directly this post from blog, I would suggest to go through this blog which helps to understand the sequence of different floorplan topic:

Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights

Before starting macro-placement, Below are the assumptions: 

• Floorplan size is reasonable with adequate initial utilization numbers
• all IO ports are placed as expected 
• all Placement blockages from FullChip (based on top-down approach) perspective is already there in floorplan 
• Design is Single power domain

Lets try to understand practical significance of  each Macro placement guideline on by one.

1. Grouping of Macros 

• Consider a scenarios where there are more than 100 Macros. In this case, first step is to identify the group of macros.
• One simple way for macro grouping is based on Hierarchical naming convention.
• If Macros are having name such as RAM_1, ABC_1, PGR_1, RAM_2,PGR_2,RAM_3,RAM_4,ABC_2,ABC_3,PGR_3, RAM_4 Below should be macro grouping:
• Group1 : RAM_1, RAM_2, RAM_3, RAM_4
• Group2 : PGR_1, PGR_2, PGR_3 
• Group3 : ABC_1, ABC_2,ABC_3
• Macro grouping can be identified using macro-to-macro connectivity as well.

2. Identify the connectivity between ports<-->macro and macro<-->macro :

• Connectivity of Macros to respective ports/other macros can be identified using Three approaches. 1. Based on data-flow Diagram 2. Based on Flyline 3. Based on standard command all_fanin/all_fanout.
• Based on data-flow Diagram:
• For given block, Frond-end designer will have Architectural diagram of Data-flow. It explains how data is transferring from Inputs port --> logic --> macro --> logic --> output ports. If data-flow diagram is not available, need to use below method. 
• Based on Flyline: 
• Generally PNR tools such as Synopsys ICC2,Cadence Innovous, can represent macro connectivity based on Flyline.  using Flyline tool, macro to respective port and respective other macro connectivity is identified by doin required configurations in Flyline tool.
• Based on fanin/fanout cone : 
• EDA PNR tools have automated commands to get the list of fanin/fanout cone.
• By default, Flyline can show the 1st level connection between macros/port. If any macro is connected to any other ports/macro at 2nd level (i.e. Macro1 --> flop --> macro2 or Macro --> flop --> port), this kind of connection is identified using fanin/fanout commands.
• fanin cone:
• suppose you want to check fanin cone of any macro input pin, below approach need to be used:
• Level1 : fanin cone of given macro input pin
• Level2 : fanin cone of Level1
• Level3: fanin cone of Leve2
• If there is any other macro/port in level2/level2/level3 , those are connected.
• 
  
  
  
• all_fanout cone:
• suppose you want to check fanout cone of any macro output pin, below approach need to be used:
• Level1 : fanout cone of given macro output pin
• Level2 : fanout cone of Level1
• Level3: fanout cone of Leve2
• If there is any other macro/port in level2/level2/level3 , those are connected.

3. Minimum Spacing(channel length) for pin facing macros 

• As Macros are having large numbers of pins, its really important to keep minimum spacing required between two adjacent pin facing macros. minimum spacing depend on multiple factors such as macro pin count, macro pin layers, 
• Distance between two macros(X)     =   (Total number of macro pins x Pitch of metal layer) /  (Total number of metal layer)
• Once above distance(X) is estimated,  need to consider other parameter such as PG grid, Physical cell placement in channel.
• there should be at-least minimum two PG straps (1 for VDD and 1 for VSS) should be available to  provide power for stdcell placed in Macro channel. This will to reduce IR drop in channel.
• Also to have robustness w.r.t Latch-up(LUP) requirement , at least one column of TAP cells are required (PNR tools generally add additional columns of TAP cells in Macro channel, but if it is not added, need to ensure it)
• Avoid vertically staking of macros if macros are more taller.

4. Minimum Spacing(channel length) for non-pin facing macros 

• generally non-pin facing macros can be abutted (with 0 spacing between two macros), but  it need to be confirmed that each macro is clean w.r.t abutment checks. i.e. there shouldn't be any BEOL/FEOL drc at the abutment of two macros.
• If macros are more wider, avoid abutment as it might cause over the macro royting which leads to Signal Integrity issues.

5. Orientation

• While placing macros, Orientation is also important thing to consider as wrong orientation may leads to FEOL drc violations or Pin crisscrossing leading to  congestions/drc issues.
• For advanced node, rotating Macros by 90 Degree is not allowed as it will disorient the metal layers and can cause Complex DRC issues.
• if R0 is initial orientation, valid orientation is MX(mirror w.r.t X axis) , MY (mirror w.r.t Y axis), R180(180 degree rotation)
• Wrong orientation can lead to block the Macro pin-accessibility (if two macros are abutted and pins of one macro is touching to other macro)

• In below snap, due to wrong orientation of Macro1, Macro1 pins are abutted to Macro2.

6.fine tunings -- reduce notch , allow proper area for stdcell placement

• Once macro grouping and connectivity between macros and ports and enough channel spacing is identified, next  step is to fine tune overall macro placement.
• Goal is to have Macro placement such that its easier for stdcell connectivity.. Consider Floorplan is Sea of gates and from one gate to other gate, it should be able to reach without any abstract ..!!!
• Fine-tuning is an art which allows more flexing stdcell placement which reduces the critical changing issues such as timing/congestion.
• while fine-tunning, try to avoid notches as much as possible as it  may leads to routing challenges.
• Try to place all Macros on boundary to allow more area for stdcell placement.
• In below image, notches can be reduce to allow proper  area for stdcell placement :

7. Macro placement on Legal location:

• While placing macros, ensure that macro is placed on legal location i.e. on FinFET grid (in lower geometry) and on manufacturing grid for higher nodes such as 28nm and more).  Also while fine-tunning macros, it shouldn't go beyond block die area. This can be validated based various commands of EDA PNR  command.
• As Lower Technology nodes are more prune to routing congestion due to dense routing tracks, it is always recommend to ensure that macro pins are on respective metal track.
• It is noted that not always all location are satisfying above two condition. to consider both condition, LCM (least common multiple) need to be calculated and Macro need to be placed in multiple of LCM value. 
• Hypothetic example: assume FinFET  grid is 0.004 and metal track is 0.075.
• LCM of 4 and 6 = 300
• Macro need to be placed in multiple of 0.300
• In some case, Macro/sub-block core-to-die offset is not same as main design core-to-die offset. Below is test case. 
• for sub block pin in horizontal layers, below equation must be satisfied:
• FinFET grid (X)
• sub-block Pin layer(M) track_offset (Y1)
• sub block bottom core-to-die offset (b1)
• Top Design M layer track_offset (Y2)
• Top Design bottom core-to-die offset (b2)
• Pin layer pitch (Z)
• LCM of X and Z = A
• sub block location = b2 - Y2 + A - Y1 -b1
• to reduce complexity, Y1 and Y2  are set as 0.

8. Apply blockage/keepout

• Once macro placement is finalized, It is important to apply required Placement/Routing Blockages and Keepout margin to avoid critical issues at later stages.
• Placement blockages : It helps to control the stdcell density in Macro channel.
• Routing blockages : It helps to control the routing resources due to non-preferred routing. 
• Keepout margin: It helps to preserve some space between Macro and stdcell.
• For more details about blockages/Keepout, click on below post:

Placement and Routing Blockages: Strategies for Optimal Design Flow

9. mark them fixed

• all Macros should be marked Fixed to avoid misplaced during placement optimization. Once macro is marked as Fixed, tool will not move it during optimization.
• there are automated commands to mark macro placement fixed in all EDA PNR tools.

10. Macro PG pin should be  connected properly to design PG grid without any missing vias

• Once macro placement is Fixed, it is important to proper connection between Macro PG pins and respective layers PG stripes without any missing via.
• Partial PG connection may leads to IR drop issue

In this post i have tried to cover majority guidelines for Macro placement. If you have any other guideline which need to be considered while doing Macro placement, Please comment. That would be great to enhance the concept.

If you have any queries or suggestions , Let me know in the comments. 

I hope you find this post useful, if Yes, like and share the post with Friends and Colleagues. 

to test your fundamental related to Macro placement, check below Challenge :

Challenge 7 : Latch-up issue