Floorplan : Essential Sanity Checks before moving to next stage

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Before going to placement and further stages, its is really important that readiness of floorplan is verified which will help to reduce upcoming stage issues in subsequent stage for Physical design..

Generally all checked are done during individual steps of Floorplan, but is it also recommended to go through all checks before moving to further stages.

This is 7th topics from "Mastering Floorplan" series. If you are directly reading  this post from blog, I would suggest to go through below main post which helps to understand the sequence of different floorplan topic:

Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights

Cell row/Total Utilization

• Ensure reasonable Cells row/Total Utilization is used. aggressive utilization (>90%) can lead to unavoidable issues in later stages.
• Important point to remember :  when keepout is applied on any cell (stdcell/macro), cell area is considered with keepout.

Height/Width dimensions of Die/Core

• Die height/width : Ensure Die height/width meets Frond End of Line(FEOL) DRCs requirements
• Core width/height : ensure Core height is  in multiple of site row height and width  in multiple of site width. (for bocks having 0 IO PADs, core-area need to keep as large as possible (best case same as die area..!!)
• In advanced node,  EDA PNR tools have automated commands to verify if floorplan size is aligning to FinFET grid or not.
• If violations, try to clean it first before moving to further stages
• As FEOL DRC is superset of all the rules, even though "check_finfet_grid" is clean, it doesn't mean FEOL DRC will be 100% clean. 
• at the end of this post, steps to run early FEOL drc  is explained which will help to validate Floorplan side/macro-physical cell placement.

Port/terminal Placement

Once Floorplan size and width/height is verified, next sanity check is related to Port placement

• make all ports are placed and unplaced ports(ports placed at origin) leads to improper placement optimization.
• ensure that each ports are placed on preferred direction layer track. terminal placed on non-preferred track may leads to DRCs issues at route/signoff stage....!!
• ensure same layers terminals  are placed with adequate required spacing between them. Generally clock nets are routed with double width/double spacing so respective clock  terminals  needs to placed with double with and double spacing
• EDA PNR tools have automated commands to validate port placement.
• using such commands, you can check if there are not shorts between terminals, min spacing violations, etc.
• All Terminals should be "Fixed".

Macro placement

• ensure all Macros are placed in core area and meeting FEOL drc rules.
• Macro pins should be on preferred layer track to avoid routing drcs.
• Make sure there are no macro overlap. 
• EDA PNR tools have automated commands to check legal location of stdcells/Macro/Physical cells.
• below command is used in Synopsys ICC2 tool. there shouldn't be any violations in rules.
• ensure Macro physical status should be FIXED to avoid misplacement of macro during optimization.

Validation of Floorplan size and Macro/Physical/Spare cell placement:

• As Macro, Physical cells, Spare cells are marked Fixed during floorplan stage, it is really important that Placement of these cells are   validated based on FEOL drc perspective. This will reduce effort of  complex FEOL drcs due to Floorplan size and Physical cell placement.

• If output of above step is clean (without any violations), It would be good to go for next step.

Spare Cell (if Spare cells added in design):

• ensure each spare module consists of adequate cell reference added. 
• Visually checks the placement of Spare modules. there should be uniform horizontal/vertical distance should be present between nearest spare module.
• Ensure  Physical status of Spare cells are marked as "Fixed".
• There shouldn't be any floating input of Sparce . Input of Spare cells should be connected to TIE Low/High cells. 

 

This is all about basic sanity checks at the end of Floorplan.

If you have any queries or suggestions , Let me know in the comments. 

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