Floorplann: A Comprehensive Step-by-Step Guide"

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Floorplan is art of Physical design as mostly referred as  critical stage as quality of chip depends on how good is floorplan. If proper care is taken while doing floorplan, critical issues of subsequent stages can be reduced such as timing/congestion/EMIR/PDV related issues.

Lets try to understand step by step process involved during Floorplan.

1. Die area estimation

For larger SOCs, FullChip die area is decided in two stages:(below steps are iterative process until PPA is meet for chip.

1. Top-down approach : 
• Initial die area is estimated based on hierarchy or sub-blocks of whole design. Once initial required area is identified, sub blocks are placed as per hierarchy grouping based on high level dataflow of design architecture. Once all sub-blocks are placed properly  within estimated die area, die area is assigned to  each individual blocks.
2. bottom-up approach : 
• Once initial area is estimated for each blocks, block owner need to check if provided area is enough for block or not based on overall area of standard cell, Macros, Memories, Hard IPs. 
• It is important to note that while estimating block area, further cell addition in  upcoming subsequent stages (such as placeopt,cts,ctsopt,routeopt) needs to be considered. to consider this, terminology called "Total/Cell row Utilization" is used.  In this post, step by step process of floorplaning  for given block is explained.  

There are two types of utilization is considered :

1. Total Utilization:
• It gives the idea of how much space is occupied after placing given stdcells, macros, macro-keepout, Hard blockages    
• total utilization = (area of stdcell/macros/macro-keepout/Hard blockages)/die area
• Total utilization provides a high level overview how efficiently block area is being used.
• It is critical during  early design planning
2. Cell row utilization:
• It refers to the density of standard cells within individual placement rows in design.
• Cell row utilization = (area of stdcell)/(total available area for stdcell  )
• total available area for stdcell = (die area) - (area of Macros) - (area of macro-keepout) - (area of Hard placement blockages)
• cell row utilization becomes significance at placement and later stages where stdcell are placed within given site row. high cell row utilization in specific area leads to congestions and related issues.
• to check utilization, automated commands are available in EDA PNR  tools

• Once die area is estimated (with reasonable utilization numbers), next step is decide the required shape for block. it is often referred as "Aspect ratio" for rectangle floorplans. Aspect ratio is very critical in floorplan as it directly impacts the PPA of design.  a well-balanced aspect ratio ensures efficient utilization of area.
• In tow down approach, initial aspect ratio can be any value but based on efficient placement of macros, stdcells it can be adjustable.
• Below are few points how aspect ratio influences the floorplan:
• Placement of macros and stdcell : poorly selected  aspect  ratio leads to inefficient placement of macros/stdcell.
• routing congestion: affects the distribution of routing resources across the design. poor aspect ratio can lead to congestion issue due to inefficient placement of macros/stdcells.
• Power distribution:  very high/low aspect ratio design requires a  complex power distribution to ensure uniform power across design.
• Design complexity: design with unbalanced aspect ratio may face physical design challenges during timing optimization, cts building for latency and skew optimization

2. Height/Width dimensions of Die/Core

• For given floorplan area, there are multiple combinations of Die height/width based on Aspect ratio. Below factors are important while deciding die height/width:
• shape and size of design Macros : for multiple wider macros, it is recommended to select wider width compared to height
• Frond End of Line(FEOL) DRC : in advanced nodes, FEOL drc issues are very critical to fix during signoff stage ....!!!! 
• Once Die width/height is decided, next steps is to consider Core width/height.
• Generally For block level designs, there are no peripheral IOs hence  core can be as less as possible (it is possible to have same die/core width/height if all dimensions are properly adjusted at Full-Chip...!) 
• in EDA PNR tools , there are commands to create floorplan size.
• initialize_floorplan -control_type (core | die) -boundary { {x1 y1} {x2 y2}} -core_offset "left_core_2_die top_core_2_die right_core_2_die bottom_core_2_die" 
• such command creates floorplan size along with site rows and tracks for all metal layers.
• it also requires control type i.e. core or die. -- if set as core , boundary will be considered as  core boundary and accordingly die boundary is created based on "core_offset" 
• Below is sample cartoon floorplan shape/size created : (control type - die)

•  (control type - core)
• 
  
  
  
• Any guess why core area is not  10x10  even though command  specified for 10x10?? 
• As mentioned in previous blog, core height must be  integer multiple of site row height and core width must be integer multiple of site row width.

3. Port/terminal Placement

• Once expected Floorplan is created, next step is to place the IO ports.
• In EDA PNR tools , ports can be placed by two approach:
• auto port placement : tool will place the ports based on given constraints for all ports.
• such commands includes sets of  constraints such as layer , length/width and side for port placement. side 1 --> left side , 2 --> top side , 3 --> right , 4 --> bottom 
• manual port placement: other approach is to place each ports with user given coordinates.
• in such approach, exact coordinate for any port given.
• Once all ports are placed, it can be verifed using EDA PNR tool command. commands can be different across all EDA tools but output will similar such as shorting terminals, terminal with wrong metal-layers..

4. Macro placement

• After placing ports, next step is to place the bigger blocks such as Hard Macro, Memory, Hard IP placement.
• Before placing the macros, first thing is to identify the connection between port<->macro, macro<-->macro.  Below are general ways to identify the connections:
• macro names based on hierarchy : typically macros having similar hierarchy names belong to group and they are inter-connected. ex, top/temp/macro_1 , top/temp/macro_2
• Flyline : PNR tools have ability to represent visual connectivity  in GUI. by proper configuration of flyline tool, expected connectivity can be identified. 
• Fanin/Fanout : connectivity can also be traced based on fanin or fanout cone.
• Fanout : to get sequential endpoint of any startpoint, fanout is used.
• Fanin : to get sequential startpoint of any endpoint, fanin is used.
• Once connection is identified, next step is to place the macros. for placing macros, there are multiple guidelines are recommended to have efficient floorplan. macro placement guidelines will be discussed in upcoming blog-post.
• Once macro placement is done, make sure macros are placed properly on manufacturing grid and no overlap are present. 
• to verify the macro placement  if its legal placement, EDA PNR tools have automated commands. 
• For detail about macro placement guidelines, Please refer below link

Best Practices for Macro Placement Guideline in ASIC Physical Design

Once macro placement is done, need to add required placement/routing blockage to effectively optimization PPA.  to understand more about blockage and its practical significance -- Placement and Routing Blockages: Strategies for Optimal Design Flow

5. Physical/Special cell placement

• After macro placement, next step is to place the Physical/Special cell placement.
• details of each cells and its significance will be discussed in upcoming blog post.

Though this post was longer, Hope it was  not boring ...!!!!

I will cover details topics in upcoming posts. 

to test your practical concepts related to Floorplan terminology, check below challenges : 

 

Core width/height calculation

 

Challenge 5 : calculate total stcell count

Keep commenting regarding which specific topics related to floorplan you would like to be discussed.

Also if you have any doubt/query related to Floorplan topics, add in comments. I will try to resolve it.

References:

Synopsys IC Compile(ICC2) tool