ASIC Physical Design : Key challenges and Innovative solutions

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Before going to placement and further stages, its is really important that readiness of floorplan is verified which will help to reduce upcoming stage issues in subsequent stage for Physical design.. Generally all checked are done during individual steps of Floorplan, but is it also recommended to go through all checks before moving to further stages. This is 7th topics from " Mastering Floorplan " series. If you are directly reading  this post from blog, I would suggest to go through below main post which helps to understand the sequence of different floorplan topic: Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights Cell row/Total Utilization Ensure reasonable Cells row/Total Utilization is used. aggressive utilization (>90%) can lead to unavoidable issues in lat...

 In all Previous blog ports, step by step process of Floorplan till macro placement is explained. Now lets discuss the importance of "Physical/Special cells" in ASIC Physical Design. This is 6th topics from " Mastering Floorplan " series. If you are directly reading  this post from blog, I would suggest to go through below main post which helps to understand the sequence of different floorplan topic: Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights Physical/Special cell :     These cells which  are different then regular logical gates and  serves unique purpose in Physical Design. These cells don't contribute in logical function but its crucial  to have them in design for physical integrity and manufacturability of chip. Physical Cells :   These  are not present in input Verilog netlist are referred as Physical only cells.  These cells are generally not appeared  in Timing report and typically us...

In all Previous blogs, Floorplan terminology and requirement before starting floorplan is explained. in this article, Lets  discuss the macro placement guideline. Macro placement satisfying the set of rules will ease the physical design and reduced the challenges at subsequent stages of Physical Design flow. Generally Macros are bigger in size, which cause critical design issues leading to increase wire net delay , cross-talk , IR drop. Hence these guidelines are help to save lots of time in future stages of flow. This is 5th topics from " Mastering Floorplan " series. If you are reading directly this post from blog, I would suggest to go through this blog which helps to understand the sequence of different floorplan topic: Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights Before starting macro-placement, Below are the assumptions:  Floorplan size is reasonable with adequate initial utilization numbers all IO ports are placed as expected...

In the intricate world of Physical Design, placement and routing blockages often emerge as critical challenges as it can significantly impact the  quality of the design flow. These blockages, whether intentional or unintentional, play a pivotal role in defining the physical layout of a chip, influencing everything from timing closure to power distribution. Understanding how to effectively manage and strategize around these blockages is essential for achieving optimal design outcomes. In this blog, we will explore practical strategies and best practices to navigate placement and routing blockages, ensuring a smoother and more efficient design process while maintaining the integrity of the final product. Placement blockages Placement blockages are specific locations where placement of stdcell is restricted.  Placement Blockages are not guide to tool but it doesn't allow  PNR tools to place stdcell in given area.  By carefully managing placement blockages, designers can...

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Floorplan is art of Physical design as mostly referred as  critical stage as quality of chip depends on how good is floorplan. If proper care is taken while doing floorplan, critical issues of subsequent stages can be reduced such as timing/congestion/EMIR/PDV related issues. Lets try to understand step by step process involved during Floorplan. 1. Die area estimation For larger SOCs, FullChip die area is decided in two stages:(below steps are iterative process until PPA is meet for chip. Top-down approach :  Initial die area is estimated based on hierarchy or sub-blocks of whole design. Once initial required area is identified, sub blocks are placed as per hierarchy grouping based on high level dataflow of design architecture. Once all sub-blocks are placed properly  within estimated die area...

In previous blog post, all necessary checks before starting floorplan was explained. It is very important to understand the significance of all Floorplan term before actually starting floorplan implementation. Lets deep dive into the floorplan basic terminologies in simple words. Here are the Floorplan terms and its significance. Full-Chip: The complete design of ASIC consists of  multiple blocks, Macro, standard cell (stdcell) ,IO PAD etc. This represents the final design which will be fabricated.  Block: It is smaller portion of FullChip design typically represent a sub module of Fullchip RTL code. Die-area:  This is total Physical area of Chip including core area and surrounding.  Die area determines the overall size of Chip and iMacs he manufacturing costs. larger die area increases the manufacturing cost. This is important factor for deciding overall PPA(power, performance, area) for any chip. Die-area may be not be in multiple of site row height but it must nee...

So far  previous blog pages explain the brief about ASIC Physical design flow. For quick glance of ASIC design flow, refer :  ASIC Design Flow . Now Lets deep dive into each steps of Physical design starting with "Floorplan inputs and Prerequisites". Floorplan is the most important step in physical design implementation. it is like planning the layout of house before building it. Faulty floorplan leads to multiple challenges at subsequent stages of physical design flow such as placement, cts, routing...A good floorplan with proper Floorplan inputs sets the foundation for subsequent stages and significantly impacting the overall quality of results. Floorplan stage : Key inputs  The input for  floorplan stage are like the materials and plans you need before building a house. Below are key inputs of Floorplan : Design information :  This refers to detailed gate level netlist representation of design containing the connectivity information of all elements...