ASIC Physical Design : Key challenges and Innovative solutions

In previous blog post, all necessary checks before starting floorplan was explained. It is very important to understand the significance of all Floorplan term before actually starting floorplan implementation. Lets deep dive into the floorplan basic terminologies in simple words. Here are the Floorplan terms and its significance. Full-Chip: The complete design of ASIC consists of  multiple blocks, Macro, standard cell (stdcell) ,IO PAD etc. This represents the final design which will be fabricated.  Block: It is smaller portion of FullChip design typically represent a sub module of Fullchip RTL code. Die-area:  This is total Physical area of Chip including core area and surrounding.  Die area determines the overall size of Chip and iMacs he manufacturing costs. larger die area increases the manufacturing cost. This is important factor for deciding overall PPA(power, performance, area) for any chip. Die-area may be not be in multiple of site row height but it must nee...

So far  previous blog pages explain the brief about ASIC Physical design flow. For quick glance of ASIC design flow, refer :  ASIC Design Flow . Now Lets deep dive into each steps of Physical design starting with "Floorplan inputs and Prerequisites". Floorplan is the most important step in physical design implementation. it is like planning the layout of house before building it. Faulty floorplan leads to multiple challenges at subsequent stages of physical design flow such as placement, cts, routing...A good floorplan with proper Floorplan inputs sets the foundation for subsequent stages and significantly impacting the overall quality of results. Floorplan stage : Key inputs  The input for  floorplan stage are like the materials and plans you need before building a house. Below are key inputs of Floorplan : Design information :  This refers to detailed gate level netlist representation of design containing the connectivity information of all elements...