Placement and Routing Blockages: Strategies for Optimal Design Flow

In the intricate world of Physical Design, placement and routing blockages often emerge as critical challenges as it can significantly impact the  quality of the design flow. These blockages, whether intentional or unintentional, play a pivotal role in defining the physical layout of a chip, influencing everything from timing closure to power distribution. Understanding how to effectively manage and strategize around these blockages is essential for achieving optimal design outcomes. In this blog, we will explore practical strategies and best practices to navigate placement and routing blockages, ensuring a smoother and more efficient design process while maintaining the integrity of the final product.

Placement blockages

Placement blockages are specific locations where placement of stdcell is restricted.  Placement Blockages are not guide to tool but it doesn't allow  PNR tools to place stdcell in given area. By carefully managing placement blockages, designers can prevent congestion, improve timing performance, and maintain the overall integrity of the design.
Placement blockages can be categorized based on their purpose and behavior:
  • ICC2 support two types of Placement blockages. Area based placement blockages and Keepout-margin/Halo.
  • Below are main three types of area based Placement blockages
  1. Hard placement blockages
    • Completely restrict the placement of any cells within the defined area.
    • example: 
      • if there are unavoidable notches either due to floorplan shapes/macro placement, Hard blockages are used to prevent stdcells being placed in that notch region.
      • Restricting placement near analog or sensitive IPs
    • Command (Synopsys ICC2):
      • create_placement_blockage -bbox {x1 y1 x2 y2} -name blockage_name -type hard (default is hard)
  2. Buffer only placement blockages
    • During optimization, only buffer/inverter are placed in given soft blockages area
    • It is honored by placement stage but can not be honored during optimization or CTS.
    • usage:
      • In narrow channel which is  sensitive to Congestion/routing density due to less availability of routing tracks
      • Between two macros (with large pin count) to reduce IR drop due to placement of Complex cells such as AOI/NOR/NAND
      • in core stdcell placement area to reduce stdcell placement density (to preserve space for further stages like CTS,routing)
    • Command ( Synopsys ICC2):
      • create_placement_blockage -bbox {x1 y1 x2 y2} -name blockage_name -type allow_buffer_only -blocked_percentage 100 
      • "-blocked_percentage" is must for allow_buffer_only blockages
    • buffer_only placement blockages


  3.  Partial placement blockages
    • Partial blockages allow limited placement of standard cells within a defined area. By default, they block 100% (i.e., no placement), but designers can set a blockage percentage to allow partial cell usage in that region.
    • It is honored by placement stage but not honored by legalization,optimization,CTS.
    • Command ( Synopsys ICC2):
      • create_placement_blockage -bbox {x1 y1 x2 y2} -name blockage_name -type partial -blocked_percentage 60
      • "-blocked_percentage" is must for partial blockages
    • partial placement blockage


  4. Soft placement blockages
    • soft blockage is almost similar as partial. only difference is while creating soft blockage, "-blocked_percentage" is not necessary.

Keepout-Margin/Halo

  • This is the region around the macros/stdcell so that no other macros and standard cell can be placed near to macros boundary
  • This is created based on stdcell/macro instances and it moves when stdcell/macro is moved from one place to other place.
  • Keepout margin can be overlapped of two adjacent macros/stdcells.
  • Command ( Synopsys ICC2):
    • create_keepout_margin -type hard -outer {0.5 0.5 0.5 0.5}  [get_cells abc_*]
keepout margin

  • If macros are moved from one place to other place, respective keepout also moved (check below image)
keepout margin

Routing Blockages 

  • Routing blockages are physical constraints to guide or restrict the tool for placement of routing resources such as metal layers, metal vias etc.
  • Routing blockages are used to archive specific design goals such as timing,power,DRC.
  • usage:
    • in crosstalk sensitive region , to prevent more numbers nets 
    • macro protection : Hard routing blockages are placed around macros to prevent routing over/near to macros.
    • High Density routing area : soft routing blockages applied in high dense area to guide tool to route in other region to reduce congestion.
  • Command ( Synopsys ICC2):
    • create_routing_blockage -layers {M1 VIA4} -boundary {{0 0} {50 0} {50 50} {100 50} {100 100} {0 100}} -net_types ( clock, signal | power | ground | scan | reset)  [ default is all net types ]
  • Practical examples :
  • In below example, to prevent M4 layer routing over and left side of macro, routing blockage is created. there are notch(U shapes area) are pins of macro where routing block is pruned to allow macro pin connection.
routing blockage

  • If there is specific region where you don't want to route any Clock net , simple thing is to add routing block w.r.t Clock nets. after CTS is done, this routing blockage can be removed to allow signal net routing.

Also if you have any doubt/query related to this, add in comments. I will try to resolve it.

References:
Synopsys IC Compile(ICC2) tool
    

Comments

Post a Comment

Most viewed

A quick glance to ASIC design flow

Image
 Hi All, Here is basic and simple  understanding of ASIC( Application specific integrated circuit ) design flow. 1.  Specification : For any ASIC design, first and main important step is "specification" .  to give simple analogy, this is the main requirement/target of design. for example , to prepare any recipe, its important to know which recipe you are going to make and what is your expectation i.e. taste,..etc. for ASIC , specification  can be no. if inputs/outputs , speed, etc...  2. A rchitectural implementation : this is high level step to define your design. this is the step where initial specifications are converted into an algorithm/code which satisfy the specification. in digital system words, this is RTL(register transfer language) implementation .  3. RTL verification : this is step to validate the earlier written algorithm/RTL code. in layman language, this process confirms that actual output of given algorithm/RTL code with the origina...
Read more

Introduction to ASIC- Physical Design

Hello All,  I am creating this blog to help all Physical Design Enthusiasts to gain knowledge on physical design fundamental concepts. On this blog spot ,  i will post all technical topics/queries and its solution. stating with ASIC flow and followed by each steps of Physical design in detail. (I will not cover very basic detail which are available in Google). I will try to make more practical approach which will help  to corelate Theory and Practical concepts. To get early updates/notifications of Posts and Frequent technical capsules, please subscribe. For frequent challenging question, I have create one group in LinkedIn: Click here to join the group :   ASIC Physical Design Enthusiasts If you have any suggestion for topic , Please share in comment box. if you have any doubt/query related to any topic, add in comment and i will share my views.
Read more

Why Order Matters: Understanding the Sequence of ASIC Design Stages

 Hi All, In the previous blog pages, we have extensively discussed the introduction of the ASIC design flow.( Please go through previous pages if not visited earlier) Each step in the flow holds its own unique significance and plays a critical role in the overall process.  But have you ever paused to consider the importance of the sequence of these stages ? Why is the order of these steps so crucial? in this blog, I delve into the reasoning behind specific ordering of the stages in ASIC design flow. 1. "DFT" :  why it is imperative to perform DFT only after Synthesis stage ..? why can't it be executed  earlier, i.e. right after RTL implementation ? Ans.  DFT is step to add  test logic  by implementing scan chain between two flops. at RTL level,  design is still high level abstract form and specific gate to flop interactions are not yet defined.  Synthesis translates RTL into gate-level netlist which provides necessary details for DFT insertio...
Read more