Placement and Routing Blockages: Strategies for Optimal Design Flow

In the intricate world of Physical Design, placement and routing blockages often emerge as critical challenges as it can significantly impact the  quality of the design flow. These blockages, whether intentional or unintentional, play a pivotal role in defining the physical layout of a chip, influencing everything from timing closure to power distribution. Understanding how to effectively manage and strategize around these blockages is essential for achieving optimal design outcomes. In this blog, we will explore practical strategies and best practices to navigate placement and routing blockages, ensuring a smoother and more efficient design process while maintaining the integrity of the final product.

Placement blockages

Placement blockages are specific locations where placement of stdcell is restricted.  Placement Blockages are not guide to tool but it doesn't allow  PNR tools to place stdcell in given area. By carefully managing placement blockages, designers can prevent congestion, improve timing performance, and maintain the overall integrity of the design.

Placement blockages can be categorized based on their purpose and behavior:

• Generally EDA PNR tools support two types of Placement blockages. Area based placement blockages and Keepout-margin/Halo.
• Below are main three types of area based Placement blockages

1. Hard placement blockages
• Completely restrict the placement of any cells within the defined area.
• example: 
• if there are unavoidable notches either due to floorplan shapes/macro placement, Hard blockages are used to prevent stdcells being placed in that notch region.
• Restricting placement near analog or sensitive IPs
• EDA PNR tools have automated commands to create Hard placement blockages. 
2. Buffer only placement blockages
• During optimization, only buffer/inverter are placed in given soft blockages area
• It is honored by placement stage but can not be honored during optimization or CTS.
• usage:
• In narrow channel which is  sensitive to Congestion/routing density due to less availability of routing tracks
• Between two macros (with large pin count) to reduce IR drop due to placement of Complex cells such as AOI/NOR/NAND
• in core stdcell placement area to reduce stdcell placement density (to preserve space for further stages like CTS,routing)
• EDA PNR tools have automated commands to create Buffer only  placement blockages. 
• to have buffer only blockages, blocked percentage is must required.
• Below is cartoon dummy floorplan illustrating buffer only blockages.
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3.  Partial placement blockages
• Partial blockages allow limited placement of standard cells within a defined area. By default, they block 100% (i.e., no placement), but designers can set a blockage percentage to allow partial cell usage in that region.
• It is honored by placement stage but not honored by legalization, optimization, CTS.
• EDA PNR tools have automated commands to create Partial placement blockages. 
• to have partial blockages, blocked percentage is must required.
• Below is cartoon dummy floorplan illustrating Partial  blockages.
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4. Soft placement blockages

• soft blockage is almost similar as partial. only difference is while creating soft blockage, "blocked percentage" is not necessary.

Keepout-Margin/Halo

• This is the region around the macros/stdcell so that no other macros and standard cell can be placed near to macros boundary
• This is created based on stdcell/macro instances and it moves when stdcell/macro is moved from one place to other place.
• Keepout margin can be overlapped of two adjacent macros/stdcells.
• Note that when keepout is applied on any stdcell/macro, its area will be considered along with keepout area (i.e. new area = (area from macro/stdcell LEF) + (keepout area) 
• EDA PNR tools have automated commands to create Keepout-Margin/Halo. 
• keepout can be created outer or inner based on requirement.
• Below is cartoon dummy floorplan illustrating outer keepout.

• If macros are moved from one place to other place, respective keepout also moved (check below image)

Routing Blockages 

• Routing blockages are physical constraints to guide or restrict the tool for placement of routing resources such as metal layers, metal vias etc.
• Routing blockages are used to archive specific design goals such as timing,power,DRC.
• usage:
• in crosstalk sensitive region , to prevent more numbers nets 
• macro protection : Hard routing blockages are placed around macros to prevent routing over/near to macros.
• High Density routing area : soft routing blockages applied in high dense area to guide tool to route in other region to reduce congestion.
• EDA PNR tools have automated commands to create Keepout-Margin/Halo. 
• routing blockages can be created for any signal/clock/scan/PG nets. it requires layer and boundary in which routing blockages need to be created.
• Below is cartoon dummy floorplan illustrating routing blockage is created on Macro pin.
• In below example, to prevent M4 layer routing over and left side of macro, routing blockage is created. there are notch(U shapes area) are pins of macro where routing block is pruned to allow macro pin connection.

• If there is specific region where you don't want to route any Clock net , simple thing is to add routing block w.r.t Clock nets. after CTS is done, this routing blockage can be removed to allow signal net routing.

Also if you have any doubt/query related to this, add in comments. I will try to resolve it.