Physical Synthesis Vs Logical Synthesis

 In Previous post, I have explained the importance of Logical synthesis. If you have not explored it, Please click below link to check it:

Synthesis : The Soul of Physical Design

In this post, Lets understand Practical significance of Physical synthesis. will understand each aspects of physical synthesis in comparison with Physical synthesis.

Physical aware Synthesis

As Synthesis(logic Synthesis) is Soul of Physical design and bridges gap between RTL and Physical implementation, Physical Synthesis bridges gap between Logical Synthesis and physical implementation. 

Regular Physical Synthesis Flow:

• This is two step process. first logical synthesis is performed and using this synthesized netlist, Floorplan and macro/port placement is done. after Power-plan, DEF file is generated which contains Floorplan information and Macro/port placement along with PG grid.
• along with DEF file, other physical inputs are provided for Physical synthesis.
• output of Physical synthesis is synthesized netlist and DEF file. This synthesized netlist is Physical aware optimized netlist and it is  different from previous logical synthesis. DEF file contains the stdcell placement information.
• Physical synthesized netlist and DEF file are used in PNR. 

Advanced Physical Synthesis flow:

• in Advanced Physical synthesis, whole process is done at a single flow which is more convenient.
• latest EDA tools for PNR supports this flow which eliminates the reequipments of separate Synthesis and PNR tools.
• first timing/Physical libs are read along with technology files. then Floorplan size/shape created along with Macro and port placement. PG grid is added followed by Physical and Special cells addition.
• after that constraints file and RC coefficient files (.tluplus) are used for Physical aware synthesis. after Physical synthesis, Placement optimization is performed.

Logical Synthesis v/s Physical Synthesis: Key Differences

• Logical synthesis focuses on transforming RTL into gate-level netlist optimizing for Power, Performance, Area. However, it does not consider the Physical layout information of Design such as actual placement of Ports,Cells and interconnects. This leads to inaccuracy in Timing and Congestion analysis.
• On other hand, Physical synthesis incorporates the Physical Layout information into optimization process which ensures that design is not only logically correct but also Physically reliable with accurate Power, Performance, Area. 
• Below are few key difference between Logical synthesis and Physical synthesis:
• Placement aware optimization :
• while optimization, Physical synthesis optimize the placement of cells to reduce wire delay and improve timing. 
• example : In digital signal processing designs, multiplier and adder are generally used in arithmetic operation. Physical synthesis places these objects nearby to reduce wire-delay between them.
• Virtual net routing using actual RC coefficient files:
•  Logical synthesis uses wire delay based models to estimate the net delay while Physical synthesis does virtual routes based on  real cell placement and net delays are calculated based on actual length along with RC coefficient files.  Hence, net delays are more accurate in case of Physical synthesis.
• example : design with non-regular aspect ratios ( >>1 or <<1 ) , for larger physical distance, Physical synthesis does better optimization compared to logical synthesis,
• High Fanout net (HFN) synthesis :
• high fanout nets such as Set/Reset signals are handled by physical  synthesis considering physical distance and creating proper buffer tree while logical synthesis only does HFN synthesis based on wire load modes (WLMs).
• example : design with Set/Reset signals driving thousands of flops, Physical synthesis ensures signal reaches with minimum delay possible with better transition on added buffers.
• Congestion handling:
• As logical synthesis doesn't have cell placement information, it can not help to reduce congestion. while Physical synthesis  identifies and reduce the congestion by spreading the cells in congested region.
• Advanced EDA tool can do Congestion driven optimization to reduce congestion and timing concurrently.
• Timing driven optimization:
• as logical synthesis used WLMs and estimated transition based cells delay, timing numbers can have significant difference in Placement stage of PNR while Physical synthesis does timing optimization by considering actual placement and routing net delays. it also adjust the placement of cells and sizing of cells to optimize timing in better way.
• Physical synthesis also fixed post layout timing issues.
• example : in high speed design , very less data-path delays are required. Physical synthesis prioritizes critical timing paths and optimize the cells placement along with cell sizing.
• Power optimization:
• Physical synthesis optimized switching and internal power by reducing output net load as much as possible. in order to do that, it minimizes the interconnect length. 
• It also does Physical aware clock gate placement and cloning to meet critical reg2EN paths. cloning of clock-gates also help to reduce the clock latency as cloning reduces number of clock cell level.
• Multibit flops : Physical synthesis can merge near-by flops into multibit flops which helps in area and power reduction.
• Runtime :
• As physical synthesis uses physical data, physical synthesis runtime is slightly more compared to logical synthesis. however, this bit increased runtime can really reduce the large turn around time in Timing/congestion closure in complex design.

Practical test case:

• consider one design as below. it contains 1 module instantiated 4 times and each modules needs to placed on 4 corners (with difference orientations) of blocks as those modules are main driver for other blocks.
• refer below floorplan :

For Logical synthesis, all 4 instances are considering together as below:

• As Logic synthesis doesn't have placement information of these modules, it can not use cloning and other optimization technology as oppose to Physical synthesis. Physical synthesis optimize common logic properly by using various optimization techniques such as cloning and register replication in common logic module. (user can control further to achieve desired output)

so far, i have observed that Physical synthesis is always better in majority cases and it help to reduce overall design closure cycle. Please let me know if you ever observed or noticed any drawbacks of Physical synthesis.

If you have any queries or suggestions , Let me know in the comments.