Mastering Floorplanning: A Comprehensive Step-by-Step Guide"

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Floorplan is art of Physical design as mostly referred as  critical stage as quality of chip depends on how good is floorplan. If proper care is taken while doing floorplan, critical issues of subsequent stages can be reduced such as timing/congestion/EMIR/PDV related issues.

Lets try to understand step by step process involved during Floorplan.

1. Die area estimation

For larger SOCs, FullChip die area is decided in two stages:(below steps are iterative process until PPA is meet for chip.
  1. Top-down approach : 
    • Initial die area is estimated based on hierarchy or sub-blocks of whole design. Once initial required area is identified, sub blocks are placed as per hierarchy grouping based on high level dataflow of design architecture. Once all sub-blocks are placed properly  within estimated die area, die area is assigned to  each individual blocks.
  2. bottom-up approach : 
    • Once initial area is estimated for each blocks, block owner need to check if provided area is enough for block or not based on overall area of standard cell, Macros, Memories, Hard IPs. 
    • It is important to note that while estimating block area, further cell addition in  upcoming subsequent stages (such as placeopt,cts,ctsopt,routeopt) needs to be considered. to consider this, terminology called "Total/Cell row Utilization" is used.  In this post, step by step process of floorplaning  for given block is explained.  
There are two types of utilization is considered :
  1. Total Utilization:
    • It gives the idea of how much space is occupied after placing given stdcells, macros, macro-keepout, Hard blockages    
    • total utilization = (area of stdcell/macros/macro-keepout/Hard blockages)/die area
    • Total utilization provides a high level overview how efficiently block area is being used.
    • It is critical during  early design planning
  2. Cell row utilization:
    • It refers to the density of standard cells within individual placement rows in design.
    • Cell row utilization = (area of stdcell)/(total available area for stdcell  )
    • total available area for stdcell = (die area) - (area of Macros) - (area of macro-keepout) - (area of Hard placement blockages)
    • cell row utilization becomes significance at placement and later stages where stdcell are placed within given site row. high cell row utilization in specific area leads to congestions and related issues.
    • to check utilization, below command is used in Synopsys ICC2
      • report_utilization

  • Once die area is estimated (with reasonable utilization numbers), next step is decide the required shape for block. it is often referred as "Aspect ratio" for rectangle floorplans. Aspect ratio is very critical in floorplan as it directly impacts the PPA of design.  a well-balanced aspect ratio ensures efficient utilization of area.
  • In tow down approach, initial aspect ratio can be any value but based on efficient placement of macros, stdcells it can be adjustable.
  • Below are few points how aspect ratio influences the floorplan:
    • Placement of macros and stdcell : poorly selected  aspect  ratio leads to inefficient placement of macros/stdcell.
    • routing congestion: affects the distribution of routing resources across the design. poor aspect ratio can lead to congestion issue due to inefficient placement of macros/stdcells.
    • Power distribution:  very high/low aspect ratio design requires a  complex power distribution to ensure uniform power across design.
    • Design complexity: design with unbalanced aspect ratio may face physical design challenges during timing optimization, cts building for latency and skew optimization

2. Height/Width dimensions of Die/Core

  • For given floorplan area, there are multiple combinations of Die height/width based on Aspect ratio. Below factors are important while deciding die height/width:
    • shape and size of design Macros : for multiple wider macros, it is recommended to select wider width compared to height
    • Frond End of Line(FEOL) DRC : in advanced nodes, FEOL drc issues are very critical to fix during signoff stage ....!!!! 
  • Once Die width/height is decided, next steps is to consider Core width/height.
    • Generally For block level designs, there are no peripheral IOs hence  core can be as less as possible (it is possible to have same die/core width/height if all dimensions are properly adjusted at Full-Chip...!) 
  • Below is basic example how to create Floorplan size in Synopsys ICC2 tool
  • initialize_floorplan -control_type (core | die) -boundary { {x1 y1} {x2 y2}} -core_offset "left_core_2_die top_core_2_die right_core_2_die bottom_core_2_die" 
    • This command creates floorplan size along with site rows and tracks for all metal layers.
    • control type -- if set as core (default), boundary will be considered as  core boundary and accordingly die boundary is created based on "core_offset" 
    • Below is one sample command and its output:
    • initialize_floorplan -control_type die -boundary {{0 0}{10 10}} -core_offset "0.2 0.5 0.2 0.5"
Floorplan die control
    • initialize_floorplan -control_type core -boundary {{0 0}{10 10}} -core_offset "0.2 0.5 0.2 0.5"
    • Floorplan control core


    • Any guess why core area is not  10x10  even though command  specified for 10x10?? 
      • As mentioned in previous blog, core height must be  integer multiple of site row height and core width must be integer multiple of site row width.

3. Port/terminal Placement

  • Once expected Floorplan is created, next step is to place the IO ports.
  • In Synopsys ICC2 , ports can be placed by two approach:
    • auto port placement : tool will place the ports based on given constraints.
      •  set_block_pin_constraints -allowed_layers {M4}  -self   -sides 1 -length 0.3 -width 0.05
        • above command sets the constraints such as layer , length/width and side for port placement. side 1 --> left side , 2 --> top side , 3 --> right , 4 --> bottom 
      • place_pin  -self -ports [get_ports *] 
        • This command actually place the ports. 
    • manual port placement: other approach is to place each ports with user given coordinates.
      • create_terminal -port [get_ports a] -object [create_shape -layer M4 -boundary {0 1 0.3 1.05} -shape_type rect]
      • above command will place the port a in M4 layers with length as 0.3 and width as  0.05.
  • Once all ports are placed, it can be verifiy using below Synopsys ICC2 command:
    • check_pin_placement  -pin_spacing true 

4. Macro placement

  • After placing ports, next step is to place the bigger blocks such as Hard Macro, Memory, Hard IP placement.
  • Before placing the macros, first thing is to identify the connection between port<->macro, macro<-->macro.  Below are general ways to identify the connections:
    • macro names based on hierarchy : typically macros having similar hierarchy names belong to group and they are inter-connected. ex, top/temp/macro_1 , top/temp/macro_2
    • Flyline : PNR tools have ability to represent visual connectivity  in GUI. by proper configuration of flyline tool, expected connectivity can be identified. 
    • Fanin/Fanout : connecitivty can also be traced based on fanin or fanout.
      • Fanout : all_fanout -from <from_pin> -endpoints_only (  "from_pin"  can be given as input ports or macro output pins and this commands returns outputs as connected sequential pins in fanout cone of "from_pin".
      • Fanin : all_fanin -to <to_pin> -startpoints_only (  "to_pin"  can be given as output ports or macro input pins and this commands returns outputs as connected sequential pins in fanin cone of "to_pin".
  • Once connection is identified, next step is to place the macros. for placing macros, there are multiple guidelines are recommended to have efficient floorplan. macro placement guidelines will be discussed in upcoming blog-post.
  • Once macro placement is done, make sure macros are placed properly on manufacturing grid and no overlap are present. 
  • to verify the macro placement  at legal placement, Synopsys ICC2 command "check_legality" is used. 

5. Physical/Special cell placement

  • After macro placement, next step is to place the Physical/Special cell placement.
  • details of each cells and its significance will be discussed in upcoming blog post.

Though this post was length, Hope it was  not boring ...!!!!
I will cover details topics in upcoming posts. 

Keep commenting regarding which specific topics related to floorplan you would like to be discussed.
Also if you have any doubt/query related to Floorplan topics, add in comments. I will try to resolve it.

References:
Synopsys IC Compile(ICC2) tool

Comments

Post a Comment

Most viewed

A quick glance to ASIC design flow

Image
 Hi All, Here is basic and simple  understanding of ASIC( Application specific integrated circuit ) design flow. 1.  Specification : For any ASIC design, first and main important step is "specification" .  to give simple analogy, this is the main requirement/target of design. for example , to prepare any recipe, its important to know which recipe you are going to make and what is your expectation i.e. taste,..etc. for ASIC , specification  can be no. if inputs/outputs , speed, etc...  2. A rchitectural implementation : this is high level step to define your design. this is the step where initial specifications are converted into an algorithm/code which satisfy the specification. in digital system words, this is RTL(register transfer language) implementation .  3. RTL verification : this is step to validate the earlier written algorithm/RTL code. in layman language, this process confirms that actual output of given algorithm/RTL code with the origina...
Read more

Introduction to ASIC- Physical Design

Hello All,  I am creating this blog to help all Physical Design Enthusiasts to gain knowledge on physical design fundamental concepts. On this blog spot ,  i will post all technical topics/queries and its solution. stating with ASIC flow and followed by each steps of Physical design in detail. (I will not cover very basic detail which are available in Google). I will try to make more practical approach which will help  to corelate Theory and Practical concepts. To get early updates/notifications of Posts and Frequent technical capsules, please subscribe. For frequent challenging question, I have create one group in LinkedIn: Click here to join the group :   ASIC Physical Design Enthusiasts If you have any suggestion for topic , Please share in comment box. if you have any doubt/query related to any topic, add in comment and i will share my views.
Read more

Why Order Matters: Understanding the Sequence of ASIC Design Stages

 Hi All, In the previous blog pages, we have extensively discussed the introduction of the ASIC design flow.( Please go through previous pages if not visited earlier) Each step in the flow holds its own unique significance and plays a critical role in the overall process.  But have you ever paused to consider the importance of the sequence of these stages ? Why is the order of these steps so crucial? in this blog, I delve into the reasoning behind specific ordering of the stages in ASIC design flow. 1. "DFT" :  why it is imperative to perform DFT only after Synthesis stage ..? why can't it be executed  earlier, i.e. right after RTL implementation ? Ans.  DFT is step to add  test logic  by implementing scan chain between two flops. at RTL level,  design is still high level abstract form and specific gate to flop interactions are not yet defined.  Synthesis translates RTL into gate-level netlist which provides necessary details for DFT insertio...
Read more