Floorplan Basics: Learn the Terms Without the Complexity

In previous blog post, all necessary checks before starting floorplan was explained. It is very important to understand the significance of all Floorplan term before actually starting floorplan implementation. Lets deep dive into the floorplan basic terminologies in simple words.


Floorplan Terms
Here are the Floorplan terms and its significance.

  • Full-Chip:

    • The complete design of ASIC consists of  multiple blocks, Macro, standard cell (stdcell) ,IO PAD etc. This represents the final design which will be fabricated. 

  • Block:

    • It is smaller portion of FullChip design typically represent a sub module of Fullchip RTL code.

  • Die-area: 

    • This is total Physical area of Chip including core area and surrounding. 
    • Die area determines the overall size of Chip and iMacs he manufacturing costs. larger die area increases the manufacturing cost.
    • This is important factor for deciding overall PPA(power, performance, area) for any chip.
    • Die-area may be not be in multiple of site row height but it must needs to be in multiple of FinFET grid/manufacturing grid.

  • Aspect ratio

    • This gives the idea about shape of rectangle  Chip/Block. for rectilinear shapes , aspect ratios is not defined as there are more than 4 edges.
    • Aspect ratio = height / width
    • Aspect ratio :1 specify the shape as square i.e. width and height same
    • Aspect ratio : >1 represents the taller design
    • Aspect ratio : <1 represent the wider design
    • as per above snap, aspect ratio would be ~1 as the design shape is squarish. 

  • Core area

    • It is the actual region of block/chip where stdcell/macro and other functional devices are placed.
    • core area can be same or less than die area but it can't be more than die area.
    • core area must be in multiple of site row height.

  • Grid : There are mainly 3 types of grids available.

    1. Manufacturing Grid:
      •  It is smallest size of measurement/resolution which can be used to define any geometry during manufacturing process. 
      • It is defined in technology file. For advances nodes, manufacturing grid can be as small as 0.001 microns while for older nodes it can be as large as 0.005
    2. FinFET grid: 
      • FinFET grid is specifically used in FinFET based designs in advances nodes (e.g. 16nm,11nm,7nm and beyond). FinFET grid ensures the placement of FIN in FinFET structure.
      • FinFET grid must needs to be aligned with Manufacturing grid.
      • in above image, FinFET grid is represented in blue grid.
    3. Routing grid : 
      • Routing grid refers to uniform grid which is used for routing interconnects . each metal layers may have its own routing grid (defined in technology file). 
      • Routing grid must needs to be aligned with Manufacturing grid,
      • Routing grid helps EDA tools to place wires/routes for better optimization.

  • Core to die offset

    • It is the distance between die edge to core area. sometimes this area is reserved for PG ring to provide uniform power to chip.
    • core to die offset must be in multiple of Manufacturing grid. for advanced nodes , core to die offset must be in multiple of FinFET grid.
    • For rectangle block, all 4 sides of offsets (left/right/top/bottom) can be different.

  • Layer track : For each metal layers in technology, it defined the uniform grid withing which respective layer shapes needs to be routed. Below are the characteristics of track. In above image, tracks and relative Terms are represented in purple color.

    • preferred direction : each layer tracks have two direction. preferred direction and non-preferred direction. By default this information is not present in technology file and user needs to assign respective direction to each track.
    • min width : minimum width of routing shape that can be routed on single track.
    • min spacing : it is the minimum spacing between two same layer routing shapes of adjacent tracks.
    • Pitch : center-to-center distance between two adjacent tracks.
      • Pitch = min width + min spacing
    • track-offset : distance from core edge to first track in preferred direction. user can set any track offset value based on requirement. there is no hard restriction.

  • Site row : This is the row in core area where standard cell is placed. site row must needs to be in multiple of Manufacturing/FinFET grid. Below are property of site row:

    • site row height : It is vertical dimension of site row and it represents minimum height of standard cells.  
    • site row width : It is horizontal dimension of site row and it represents minimum width of smallest standard cells.  each technology should have FILLER cells with minimum 1x row width. 
    • site row orientation : The direction in which cells in a row are placed. for example N (north) , FS (Flip South). 

  • Port :

    • It is logical definition of IOs of Verilog module in gate-level netlist. In below example, i1,i2 are input ports while o1,o2 are output ports.
module abc (i1 ,i2 ,o1 , o2);
input i1 ;
input i2 ; 
output o1 ;
output o2;

  • Terminal:

    • It is physical representation of port. It contains property such as layer/width/length.
    • for any port, there can be multiple terminal exists.

  • Stdcell (Standard Cell):

    • A predefined logic cells which has height as multiple of site row.
    • All such cells have  height in integer multiple of minimum height (same as site row)  hence it is  referred as "standard" cell ...! 

  • Macro 

    • A Large predefined block such as memory/PLL/custom logic.
    • Macro must needs to be placed on manufacturing/FinFET grid. it may not be placed aligning with site row.

  • Keepout

    • a region in core area where no stdcells are allowed. generally it is applied on specific stdcell/macros to avoid density/congestion issues. 
    • Keepout can be applied on all 4 direction (top.bottom,left,right)
    • Keepout margin of two stdcell can be overlapped. 

  • Halo

    • a region around macro where  no other stdcell cells are allowed.
    • Halo of two macros can be overlapped (if two macros are abutted )

  • Placement blockage : Area in core where placement of stdcell/macros restricted. Placement blockage have property as name, boundary, blockage type, blockage percentage (for partial blockage). There are mainly three types of placement blockages exits :

    • Hard placement blockage : there is complete restriction of any cells in that area.
    • soft/Partial placement blockages : There is partial restriction (defined as percentage) of any cells in that area.
    • buffer only blockages : there is complete restriction of any cells other than buffer/invertors  in that area.

  • Routing blockages:

    • It is used to restrict certain routing layers in given area. 
    • Routing blockage have property as name, boundary, layer name


I have tried to cover majority Floorplan Terms. Please comment if i missed any.

For above mentioned terms, if you have any doubt/query or other interesting fact, Please share in comment.

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