PowerPlan : basic introduction

 Hi All,

Hope you have gone through posts related to Flooroplan and Synthesis.

Lets understand importance of PowerPlan in ASIC design flow.

PowerPlan

• In older Technology nodes, main priorities were given to Timing and Area because these parameters  were dominant over power . however in lower nodes, as devices are shrinking there are more numbers of devices in same area.
• Also to supply power to these smaller devices, Power supply also becoming smaller over a time ( consider mobile batteries. its size keep reducing in last 10 years..!!! and also supply power is also reduced i.e. in older nodes, supply voltage in range of 1.5-2 V while it is drastically reducing now a days within 0.6-0.8 range). 
• in lower nodes, to address complex timing challenges power consumption is increasing   hence in  power is more dominant over area and timing. 

Terminologies

• Power PAD : it is source from where chip get the power from external world. for wire-bounding Technology, Power PADs are placed at the periphery of Chip.
• Power Bumps : it is source from where chip get the power from external world. for wire-bounding Technology, Power PADs are placed inside Chip..
• Power Rings: from Power PADs Power is distributed uniformly using Power Rings. Power rings are place around the core periphery of chip.
• Power stripes: Power is further distributed from power ring using power straps. generally power stripes are preferred in higher layers as higher layers have more thickness which helps to reduce Resistance which eventually helps in reducing IR drop.
• Power stubs: Power stubs are stripes having smaller length. having straps in all the layers, leads to very little routing resources availability. also longer routes leads to additional DRC rules (such as, spacing requirement is more when parallel length between shapes increases)
• Power rails: Power rails is also one kind of stripes but it is in bottom most layers. as stdcell have power/ground pins in lower layers and to connect those pins, power tripe in that layer is referred as power rail. Power/Ground rails should be aligned with site rows. 
• Power VIAs: to connect two power/ground objects such as ring, stripes, stubs, rails Power/ground vias are used. generally these VIAs are different compared to signal VIAs. Power/Ground VIAs are generally in bigger size also it is multi-cut ( contain multiple rows and columns of via cuts) to have less resistance.

Power supply connection types

• ASIC chip can be connected to substrate using two methods:
• Wire bounding
• In this technology, wires are used to connect chip to substrate.
• It is simpler and less expensive and used for lower performance chips.
• due to longer wire distance, it consumes bit more power dissipation.
• It is used in older nodes which needs low cost.
• generally Power/Ground PADs are placed at the periphery of the chip.
• Below is example of Power/Ground PADs ( Wire bounding technology) 

• From Image, it is illustrated  that power and ground PADs are placed at the edge of the chip. Chip is getting power (from outside of chip) from power/ground PADs through Power/Ground ring and eventually goes to power rails as per below order:
• Power PADs (red)
• Power rings
• Power stripes
• Power rails ( through VIAs)
• Power PADs (black)
• Ground rings
• Ground stripes
• Ground rails ( through VIAs)
• all the PADs such as Signal PADs, Power PADs, Ground PADs are placed on the edges.

• FlipChip Technology
• In this technology, Solder bumps are used to connect chip to substrate.
• Chips is flipped upside down such as solder bumps are directly aligned on substrate. hence as the connection is shorted between chip to substrate, this technology gives higher performance.
• due to short distance between chip and substrate, it consumes very less power dissipation.
• It is used in advanced nodes where higher performance is required such as Smartphones, CPUs, GPUs.
• Power/ground sources (also known as C4 bumps , Controlled collapse chip connection) are speeded equally over the chip in grid pattern across all over the chip not just the edges. 
• Below is example of PowerPlan in FlipChip technology.

• From image, it is observed that power/ground source are Bumps instead of power-plan. from bump, it goes to power tripes and eventually goes to power rail.
• This is more effective power distribution as compared to Wire bound technology as power is coming to power straps through very short distance hence there will be very less IR drop.
• Notice that, power/ground rails are cut around macros.

Power plan strategy

As input netlist contains only Signal ports and signal net connection, it can't be directly used for power plan. Below steps needs to perform first:

• create power and  ground ports
• As power can come  from outside and it might goes to other block, generally direction for power and ground ports should be defined as  "inout"
•  hence in any ASIC chip, there should be minimum 2 inout ports ( 1 power and 1 ground)
• create power and ground nets
• "connect power port with respective power net" and "connect ground port with respective ground net"
• convert  Logic 0 and Logic 1 nets to respective power and ground nets.
• input netlist contains below connections :
•  Logic 0 nets connected as 1'b0 :

 

•  Logic 1 nets connected as 1'b1 :
•  <ref_name> <instance_name> ( .D(1'b1), .CLK(pclk), .RSTB(n5), .Q(prst_ff) );
• In order to add TIE HIGH and TIE LOW cells, these 1'b0 and 1'b1 should be converted to respective power and ground nets.
• connect power nets with all power pin of cells ( it can be macros, modules, stdcell cells)
• connect ground nets with all ground pin of cells ( it can be macros, modules, stdcell cells)
• Below image illustrate all these connection:

Power-Planning steps and importance:

• If design requires power rings, try to build power rings in top two metal layers ( MTOP/MTOP-1 layers) surrounding the core area.
• If top metal for design is M19 layers, create power rings in M19 and M18 layers. 
• ring width should be as more as possible ( though it can't be higher than max width of respective layer)
• Power stripes : 

Post is not completed yet....!!!! 

update in on going. Please comment which topic you would like to be discussed w.r.t Power-Plan.