Multi Mode Multi Corner (MMMC)

MMMC (Multi-Mode Multi-Corner ) is needed in modern chip design to make sure that chip works properly in all conditions. It handles changes in manufacturing, power, temperature, and how the chip operates in different modes.

Before understanding details about MMMC, Lets try to understand its importance through below analogy.

Suppose you are making a chip which will be used in mobile. in order to have more sells all over India, it is really important that same mobile handset should work in all states including Jammu and Kashmir (J&K) , Gujarat and Kerala (Of course it will be restricted in Military area...!!). J&K is very cold area where temperature might be as low as -40 Degree while Rajasthan's Thar Desert where temperate might go as high as 40 Degree. 

other states where  average temperate is in range of 20-30 Degree. In order to have sells across India, it is really important that Mobile Handset should work properly with expected performance in all states. 

Thus, to understand simply, to make sure the Chip works properly in all condition, Chip implementation  is done considering all possible combinations of operating conditions. This is where MMMC comes into play—it helps design and test the chip for all combinations of operating conditions to ensure it works everywhere.

Fact Check : Some people refer to MMMC as MCMM. Both terms mean the same thing.

MCMC (Multi-Corner Multi-Mode) 

• Multi-Corners refers to Device variation. (its like in Vegetable market, all apples/tomatoes are not having same quality eventhough they are pla in same farm,,!!)
• Device variation is categorized  into two types. 1. Global variation 2.  Local variation. 

Global Variation : 

• It is assumed to be uniform across die but might very from die to die.
• modelled using  PVT variation (Process, Voltage, Temperature) and Extraction  variation.

PVT : 

• Process : Semiconductor Manufacturing process is not perfect and variations in process parameters are expected. for example, Die on middle of wafer may have slightly different performance compared to Die on the edge of wafer.
• Device size might very compared to ideal one (L,W) 
• Threshold Voltage variation 
• Voltage : due to power supply fluctuations, voltage level might very or due to IR drop , which might affect the performance. 
• Temperature : In order to operate chip in wide range of Temperature, It is important to test the chips for all possible temperature as Change in Temperature impact the speed of Chip. transistor devices are 'Semiconductors" , delay of semiconductor devices increases with high temperature ( for advanced lower nodes, effect of  "Temperature Inversion" also needs to be considered..!!!!)
• Based on PVTs ( Process, Voltage, Temperature) there are multiple permutations and combinations are possible but to reduce complexity best and worst cases are considered. 
• Parameter such as Mobility, Leakage depend on Temperature 
• Mobility decrease with increase with T
• Leakage increase with increase with T
• For example, in above 3D graph, each parameters are represented as a individual axis of 3D graph. each corners of cube represents possible best/worst case for PVTs. to consider all possible combinations of PVT , generally PVT values at corner of above cube is considered. i.e. min/max P , min/max V , min/max T. also the center point of cube ( Typical/Average) is considered along with min/max combinations of PVT conditions.  

Extraction variation : 

• for any net , delay depend on Resistance(R) and Capacitance(C) :
• R = rho*L/A ; rho --> resistivity of metal , L --> length
• C = eA/D      ; e --> permittivity between metal plates ; A --> metal area
• As metal layers are "Conductors", resistance increases with increase in temperature. Also Capacitance of net increases with increase in temperature.
• Based on above equation, RC models are generated to have best/worst parasitics.
• Generally below corners are used :
• Typical  -- center or nominal one
• Cworst   -- represents largest C value ( provides largest delay for shorter nets)
• RCworst -- represents largest RC product value ( provides largest delay for longer nets)
• Cbest     -- represents smallest C value ( provides smallest delay for shorter nets)
• RCbest  -- represents smallest RC product value ( provides smallest delay for longer nets)
• For Double Patterning, need to consider "Mask Misalignment" effect as well. it is modelled using below :
• CCworst -- Mask Misalignment assumes two mask are closure (higher capacitance)
• CCbest -- Mask Misalignment assumes two mask are far (less capacitance)

Local Variation : 

• Local variation refers to variation in devices on same die.
• Local variation is modeled using below :
• OCV (On Chip Variation)
• LVF libs contains different coefficient for different cells.
• Derating
• IR drop and local heating might leads to location variation.
• it is modeled using Delta V , Delta T derates.
• device functionality is also affected on devices usage over the years. it is considered using aging derates.

Above explanations mentions the significance of Corner variation. 

Mode variation : as design have have multiple operating modes, Timing constraints might be different for each modes.

Practical significance of MCMM/MMMC file:

Without MCMM file :

• In older designs, generally single mode and single corner was used as PnR implementation. but in Advanced/lower nodes, design complexity is increased and fixing violations across multiple Timing signoff corners is really difficult to fix which also increase the Signoff closure duration.

• From above image, there is only 1 scenario used in PnR. and it is corelated fine with one of Timing Scenarios. but fixing violations from one scenario leads to violations in other scenario and fixing those violations again leads to violations in other scenario..!!
• above image only shows 6 scenarios still it looks complicated. Advanced nodes design might have scenarios more than 150 ..!!!! (just think the amount of complexity in this case )
• thus adding few scenarios in PnR implementation helps to reduce this complexity. [ refer below image ]

With MCMM file :

• It is noted that by adding few scenarios in PnR implementation, reduced complexity across signoff scenarios.
• There is trade-off between PnR implementation scenarios and Signoff scenarios. not all scenarios can be added in PnR as it might increase in runtime ..!!! 
• It is recommended to use worst scenario combination from Signoff scenarios in PnR.

MCMM file example

• mode creation :
• need to create mode as per mode specific constraint. example,
• mode1 : functional mode
• mode2 : test mode
• corner creation :
• corner creation includes the ,
• corner specific TLUPLUS/RC coefficient files
• based on Cworst/RCworst/Cbest/RCbest/....
• corner specifics reference cell (stdcell, Macro/IP)  DBs linking
• PVT specification :
• Process
• Voltage
• Temperature
• OCV derating : to consider Local variations
• using above parameters, corners are created as corner1, corner2, corner3 ...
• Scenario creation :
• based on previous mode and corner creation, scenarios are created. for example,
• scenatio1 : mode1 + corner1
• scenatio2 : mode1 + corner2
• scenatio3 : mode2 + corner1
• scenatio4 : mode1 + corner3
• scenatio5 : mode2 + corner3
• scenatio6 : mode1 + corner4
• scenatio7 : mode2 + corner5
• scenatio8 : mode1 + corner5
• Scenario- analysis type definition :
•  each created scenarios might be enable for Setup/Hold/Max transition/Max capacitance/Power.
• need to mentioned the  scenario and respective active analysis type.

I hope this post explains the significance of Multi-Corner Multi-Mode analysis.

Please let me know in comment if any point i missed.

If you find this post helpful, Please like the post and share it with your friends and colleagues.