Challenge 10 : Formality

 Hi All,

Hope you have gone through Synthesis and Formal Verification posts.

to test your knowledge, Check below challenge :

In Synthesis, incase of sequential optimizations such as Register retiming and Multibit Register Banking, it can alter the structure between reference design and implemented design. this will cause Compare points mismatch  between reference design and implemented design.

What would be Formality/Logic equivalence Check result ? PASS or FAIL ?