Low Power Design

Consider below scenario:

If you have designed one smartphone very faster and less area. speed is very high (no lag) also response is quicker. but what if the device getting discharged within 30min ?  will you buy that smartphone ..?

I am assuming your answer would be a big "NO" (unless you have figured out way to reduce battery usage...!! )

Well, there are multiple such scenarios possible if you start counting... that's why requirement of "Low Power" comes into picture.

Low Power : significance 

• for advanced technology mode designs, as frequency is very high which leads to high switching which consumes more dynamic power (internal + switching power). 
• Also as devices shrinks, Leakage is more compared to older node which leads to Leakage (or standby) power.
• Thus in lower noes, along with smaller area and higher speed, it is really important to Low power.

Categories of Low power design

1. Multi-voltage design [ Power domain operates at different voltage]
• If there are multiple blocks in chip, all function of chip may not required same performance. for low performing blocks, voltage can be reduced to reduce overall power consumption.
• for example, USB and CPU module in a Chip. USB may not required high performance while CPU always needs to be operated at higher frequency. 
• here all voltage domains are referred as "Always On (AON)" domain.
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• in above image, there are two Domain A and B are Always On and operating  on different voltage.
2. Design with Switching(ON-OFF) domain [ Power domain operates at same voltage]
• If any function of chip is not required for sometime, power for same can be turned-off to save overall power consumption.
• such power domain is referred as Switching domain or ON-OFF Domain or gated domain.
• as per below image, Domain A is switching domain while domain B is Always on domain. both domains are operating at same voltage.
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3. Combination of #1 and #2
• This is mixture of type #1 and type #2.
• in this category, voltage value can be different between switching domain and Always on domain. 
• as per below image, both the domain (A and B) operates on different voltage and one of them is Switching domain.
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4. Dynamic Voltage Frequency scaling (DVFS):
• This is techniques where Voltage and frequency of design can be adjusted based on overall load.
• for low performance tasks, voltage and frequency can be reduced while for high performance task  voltage and frequency can be increased accordingly.
• This techniques commonly used in mobile, laptop to reduce overall power consumption.

Low Power : Terminologies

1. Power Domain : 
• It refers to logic partition with common power characteristics (same voltage)
• to define power intent, one of the required object is power domain information.
2. Supply nets :
• It refers to the name of power or ground nets. 
• low power design can have more than one power net.
3. Supply sets:
• It is combination of supply nets (1 power net and 1 ground net)
4. power state :
• in case of switching domain, need to define when that power domain is OFF and ON. this information is defined using power state information.
5. Power management cells/Power strategy :
• when signal crosses electrical boundary (one power domain to other power domain), special cells are used which referred as Power management(PM) cells. strategy to place such cells are refers as Power stretegy.

Below image mentions the above terminologies :

• Power domain : PD_1 and PD_1
• Supply nets      : VDD_1, VDD_2,VSS
• supply sets : 1. (VDD_1 & VSS) 2.  (VDD_2 & VSS)
• Power state : if one of the domain is Switching domain, need to define power state to explain the relation between PD_1 and PD_2

Low Power cells / Power management cells :

• When signal is travelling from one power domain to other power domain, destination cell may not work properly due to different between voltage level in both power domain.
• Hence to protect the interface between two power domains, special purpose cells are added which is referred as low power special cells or Power Management cells.  Lets understand significance of each such special cells.

Level-Shifter cells :

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• When signal is propagated from low power domain  --> high power domain  ,  high power domain --> low power domain, voltage level many not be compatible from one domain to other domain due to different voltage.
• Level-shifters ensures proper communication from one power domain to other power domain.
• example :
• A low-voltage signal (e.g., 0.8V) may not be high enough to be recognized as a valid logic 1 in the high-voltage domain (e.g., 1.2V) which leads to functional failure.
• A high-voltage signal (e.g., 1.2V) may damage the low-voltage domain circuitry if directly connected.
• level-shifter requires tow power connection, i.e. low voltage and high voltage
• Level-shifter can be placed in source power domain or destination power domain or in-between source and destination power domain. 
• by default Synthesis/PnR tool can place Level-shifters cells at anywhere. if it is required to place these cells in destination domain, need to guide tool accordingly. 
• generally Level-shifter cells can't be drive much distance so it is recommended to place them in destination power domain. (more distance might leads to more delay and timing violations!)
• level-shifter cells have two power pin. Primary power pin  and secondary power pin.
• If level-shifter is placed in high voltage domain, Primary power pin is connected to high voltage rail and secondary power pin connected to low voltage (secondary pin routing is done  similar as regular signal routing)
• below image explains the level-shifter connection between two domain.
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• Below example illustrates how secondary and primary looks if Level-shifter placed in destination domain.
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• for LV1 level-shifter : Primary  pin --> VDDH , secondary pin --> VDDL
• for LV1 level-shifter : Primary  pin --> VDDL , secondary pin --> VDDH
• Synthesis/PnR  tool can inserts Level-shifter cells if power domain crossing  is specified in UPF file.

Isolation cell

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• When any power domain is switched off, signal transferring from switching domain to Always ON domain might get corrupt as there is no exact 0 or 1 value transferred due to cell off.
• if such unpredictable value(X) is propagated to always on domain, cell inside always on domain might observe short-circuit/ Crowbar  current (due to P_MOS and N_MOS turned on) and if this happens for longer duration it might damage that device and chip.
• Isolation cells are placed at the boundary between the powered-off domain and the powered-on domain. These cells ensure that the powered-on domain receives a valid logic value (either 0 or 1) instead of a floating signal.
• Isolation cell has the control signal which sends either 0 or 1 value if switched-off domain goes to off state which ensures that cell in always on domain always receives proper 0 or 1.
• The decision to use 0 or 1 as the isolation value for isolation cells depends on the logic requirements of the powered-on domain and the functionality of the design. Thats why this information comes from RTL design.
• If control signal is 0, AND gate is used as Isolation cell
• If control signal is 1, OR gate is used as Isolation cell
• Synthesis/PnR tools can't add Isolation cells if control signal information is not provided as it might leads to functionality violation. tool can identify if any Isolation cell is missing.
• Isolation cells should be connected to Always ON power grid as it should be active even though power domain is off state. so switching domain will have two power rails. both operating at same voltage. one is always ON (main supply) and one is regular rails (virtual rail) (which can turn-on or off).
• below image illustrates how Isolation cells added at power domain crossing.
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• in Advanced designs, Isolation cells and level-shifter cells are merged as a single cell to reduce area. such merged cell is also referred as enable level-shifter cells.

Power Switch cells 

• in case of switching domain, if design goes to OFF state, it stills consumes power due to leakage current. 
• Power switch cells cut-off the power so that there is no leakage current which helps to achieve 0 leakage power during OFF state.
• This technique to reduce leakage power is called as "Power Gating".
• generally two types of power switch cells are there: Header cells and Footer cells.
• Header cell :
• Header cells are power switch cells placed between the main power supply (VDD) and the virtual power rail (VDD_V) of a block.
• When the header cell is ON, it connects the main power supply (VDD) to the block(VDD_V)
• When the header cell is OFF, it disconnects the block from the power supply( i.e. disconnect from VDD to VDD_V)
• Footer cells:
• Footer cells are power switch cells placed between the ground (VSS) and the virtual ground rail (VSS_V) of a block.
• When the footer cell is ON, it connects the block to the ground (VSS_V).
• When the footer cell is OFF, it disconnects the VSS and VSS_V.
• No. of power switch calculation:
• power switch count depend on following factoers.
1. IR drop limit for switching domain (IR) : X mV
2. current drawing requirement  : Y A
3. using #1 and #2, calculate total resistance  required (Rtot) = #1/#2
4. Resistance per power switch cell ( available in power switch lib) : Rone
5. no. of power switch = #3/#4 = Rtot/Rone

Retention cells 

• when the power to a block is turned off, Retention cells are special types of flip-flops used in low-power designs to retain their data .
• A retention cell is a flip-flop with an additional retention latch:
• When the block is powered ON, the retention cell works like a normal flip-flop
• Before the block is powered OFF, the data in the flip-flop is transferred to the retention latch.
• The retention latch is powered by a small, always-on power supply and  it keeps the data even when the main power is OFF.
• When the block is powered ON again, the data is restored from the retention latch back to the flip-flop
• Example :
• Imagine a smartphone:
• When you lock your phone, the screen and some parts of the chip are powered off to save battery.
• However, the phone still remembers your last app or screen state when you unlock it.
• Retention cells are used to save this state while the rest of the chip is powered down.

Always-ON buffers

• If any power domain is switching (ONN/OFF), and when signal is travelled through ON_OFF domain, when that switching domain goes to OFF state, it can't propagate signal properly.
•  such buffers are powered by Always ON power regardless of state of switching domain.
• Example:
• when smart-phone is goes to switched off, its power button is still active. i.e with power button device can turned on again.
• here, power button logic is placed in always ON power domain.
• If clock signal needs to go through switching domain, such clock cells are added into always ON buffers as clock should be always active regardless of state of switching domain.

Updating.....

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