ASIC Physical Design : Key challenges and Innovative solutions

****** Area Optimization ****** Suppose you have been given one design and respective Technology related files and been asked to Optimize area as much as possible considering reasonable Routing DRC numbers and reasonable Hold/Setup violations (Only Internal). Data Provided: - RTL - Technology related data You are allowed to modify below: - Constraints : Constraints file is not given. you can use any constraints requires (but dont make all paths as False paths 🙂 ...!!!) - Floorplan shape and size : any shape and size can be used - Port Placement : no port placement is given. you can place ports in any layers, any location (no ports should be unplaced..!) - any Synthesis/PnR implementation Tool can be used. Goal: - Overall area ( stdcell / Physical cells ) should be as minimum as possible - Internal Setup/Hold timing should be less than uncertainty - Routing DRC should be reasonable There are many ways possible here. Please share your approach here. Expecting Out of the B...

  **** ASIC Physical Design ECO Challenge**** Assume below scenario: Design is clean w.r.t Timing Qor/Physical Verification/EMIR. -- Base layer is Frozen. [ good for Tapout ] Timing is Clean Signoff Physical Verification is Clean EMIR is Clean Formality is PASS Due to some Functional ECO, design is opened again and new timing violations were observed. Attempted Timing violations through metal-layers optimization only. after optimization, Timing is Clean Signoff DRC is Clean Signoff ERC/LVS is clean EMIR is Clean Formality is PASS Base layer XoR is clean w.r.t before ECO Is this good to Tapout this design ? Share your answer as "Yes" or "No" in comment box. I will share my views later as first would like to give opportunities to all members to share their views.

Challenge on Setup/hold slack calculation... check below image. without crosstalk impact, setup/hold slack between FF1-->FF2 is 0ps.  with crosstalk, crosstalk of 10ps is introduced on below 3 nets.  what will be setup/hold slack considering this crosstalk effect?  #STA #Setup #Hold  #Challenge Type your answer in Comment below.

 Hi All, Hope you have gone through Synthesis and Formal Verification posts. to test your knowledge, Check below challenge : In Synthesis, incase of sequential optimizations such as Register retiming and Multibit Register Banking, it can alter the structure between reference design and implemented design. this will cause Compare points mismatch  between reference design and implemented design. What would be Formality/Logic equivalence Check result ? PASS or FAIL ?

 Hi All, check below Challenge to revise your concepts related to Floorplan. Consider one FullChip with below specification: core-to-die : 1.014 Floorplan Shape : Rectangle Max routing layers : M15 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 M5 track offset : 0.026 Consider one block from FullChip from below specification: Block level ports in M5 layers (Horizontal direction) , M5 Pitch : 0.076 M5 track offset : 0.026 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 core-to-die : 1.014 Goal: Block-A and Block B is same. (instantiated two times in FullChip) in FullChip, Both blocks orientation is R0. In FullChip, two block (Block-A and Block-B) need to be placed as vertically stacked. ( i.e. 0 Y distance between two blocks) There shouldn't be FEOL/base drc violations and Ports of both blocks should be on track. Comment How to archive...

Hi All, check below Challenge to revise your concepts related to macro placement guidelines. Consider one block with below specification: core-to-die : 0 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 Consider below Macro: Macro pins in M5 layers in Horizontal layers , Pitch : 0.076 macro width : 10um Goal: Need to Place this macro in block without having FEOL drc and macro pins should be on track. Comment what should be macro origin i.e x,y location of lower left corner. Share your answer in comment.

 Hi All, Hope you have gone through the important aspect of  Floorplan i.e. "Macro Placement". if not, Please revies your concepts by clicking below link: Best Practices for Macro Placement Guideline in ASIC Physical Design Refer below image for Challenge: MEM1/MEM2/MEM3 are same Macro with same cell reference name.  distance between MEM1-->MEM2  is same as MEM2-->MEM3. in FEOL/base DRC, Latch-up issue is reported in between MEM2-->MEM3 while there is no Latch-up issue between MEM1-->MEM2. Please think and share your views what could be reason for Latch-up between MEM2-->MEM3.

 Hi All, to test your practical concepts related to Advanced STA, I have added more challenge. what will be slack of above Timing report. Comment your answer and share your views.

 Hi All, below case will test your practical concepts related to Floorplan. suppose, there is one design without any macros/IPs with Floorplan Aspect ratio as 1. site row height as 0.169 and site row width is 0.048. in all stdcells, applied keepout : left --> 0.24  ,  right --> 0.24 . left/right side core to die offset as 0.624 and top/bottom core to die offset is 1.014. for this design placeopt is completed (stdcells are legalized properly).   After completing placeopt, all Physical/Special cells are removed manually and also stdcell apart from instances with cell reference as INV8 are removed. (i.e. design is having only INV8 ref cells). stdcell utilization : 0.6 , Total stdcell area : 476.3772 , Total Core area : 793.962 From LEF, area of INV8  : 0.15412800 -------------------------------------------------------------------------------------------------------- What will be Total stdcell count ..? comment your answer below. To revise Floor...

 Hi ASIC Physical design enthusiasts, Suppose you received a Verilog netlist ( lets say temp.v ) and designer forgot to mention the top design/module name. There are multiple ways possible to get the top module name. Which approach you will use to find the design name ?  Please share the your approach with steps. If  scripting is required, mentioned the sequence of command/algorithms. Comment your views.

Hi All, Challenge to test your Floorplan concepts. what will be Core height and width as a output of  below command ?   initialize_floorplan  -boundary {{0 0}{10 10.01}} -core_offset "0.624 1.014 0.624 1.014" Please share  your views in comment. If you need help to revise concept, refer floorplan guide : Mastering Floorplanning: A Comprehensive Step-by-Step Guide"

 Hi All, Refer below image. all the dimensions are illustrated using ruler. What will be track_offset for given layer track showed in image? Type your answer in comment box. to get explanation : Floorplan Basics: Learn the Terms Without the Complexity

Below is Timing report for Advanced STA.  What will be setup slack in below path : Post your answer of Exact slack in comment box with justification.