ASIC Physical Design : Key challenges and Innovative solutions

Consider below scenario: If you have designed one smartphone very faster and less area. speed is very high (no lag) also response is quicker. but what if the device getting discharged within 30min ?  will you buy that smartphone ..? I am assuming your answer would be a big "NO" (unless you have figured out way to reduce battery usage...!! ) Well, there are multiple such scenarios possible if you start counting... that's why requirement of "Low Power" comes into picture. Low Power : significance  for advanced technology mode designs, as frequency is very high which leads to high switching which consumes more dynamic power (internal + switching power).  Also as devices shrinks, Leakage is more compared to older node which leads to Leakage (or standby) power. Thus in lower nodes, along with smaller area and higher speed, it is really important to Low power. Categories of Low power design Multi-voltage design [ Power domain operates at different voltage] If there ar...

 Hi All, In the previous blog pages, we have extensively discussed the introduction of the ASIC design flow.( Please go through previous pages if not visited earlier) Each step in the flow holds its own unique significance and plays a critical role in the overall process.  But have you ever paused to consider the importance of the sequence of these stages ? Why is the order of these steps so crucial? in this blog, I delve into the reasoning behind specific ordering of the stages in ASIC design flow. 1. "DFT" :  why it is imperative to perform DFT only after Synthesis stage ..? why can't it be executed  earlier, i.e. right after RTL implementation ? Ans.  DFT is step to add  test logic  by implementing scan chain between two flops. at RTL level,  design is still high level abstract form and specific gate to flop interactions are not yet defined.  Synthesis translates RTL into gate-level netlist which provides necessary details for DFT insertio...

   Hi All, In previous blog, basic definition of all steps of " ASIC design flow " is explained.  Please check below lines which illustrates the analogy between " ASIC design flow " and " Music industry ". ------------------------------------------------ Analogy Between ASIC(Application-specific integrated circuit ) Design Flow and the Music Industry ASIC World : Front-End and Back-End. Music World : Song -- lyrics writing (corelates with Front-End) and Singing a song (corelates with Back-end). 1.  Specification  :    ASIC World : its related to specs of design functionality. Music World : before writing any song, its important to understand the requirement. i.e. song expressing  happy/romantic/sad/dance mood 2. A rchitectural implementation  : ASIC World :   specifications are converted into an algorithm/code which meets the design requirements. Music World : According to song requirement, high level frame work is created us...

 Hi All, Here is basic and simple  understanding of ASIC( Application specific integrated circuit ) design flow. 1.  Specification : For any ASIC design, first and main important step is "specification" .  to give simple analogy, this is the main requirement/target of design. for example , to prepare any recipe, its important to know which recipe you are going to make and what is your expectation i.e. taste,..etc. for ASIC , specification  can be no. if inputs/outputs , speed, etc...  2. A rchitectural implementation : this is high level step to define your design. this is the step where initial specifications are converted into an algorithm/code which satisfy the specification. in digital system words, this is RTL(register transfer language) implementation .  3. Functional Verification (RTL verification) : this is step to validate the earlier written algorithm/RTL code. in layman language, this process confirms that actual output of given algorithm...