Physical and Spare Cells: Foundations of Modern IC Design

 In all Previous blog ports, step by step process of Floorplan till macro placement is explained. Now lets discuss the importance of "Physical/Special cells" in ASIC Physical Design.

This is 6th topics from "Mastering Floorplan" series. If you are directly reading  this post from blog, I would suggest to go through below main post which helps to understand the sequence of different floorplan topic:

Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights

Physical/Special cell :

    These cells which  are different then regular logical gates and  serves unique purpose in Physical Design. These cells don't contribute in logical function but its crucial  to have them in design for physical integrity and manufacturability of chip.

Physical Cells : 

• These  are not present in input Verilog netlist are referred as Physical only cells. 
• These cells are generally not appeared  in Timing report and typically used to fulfill Physical requirement of Chip-finishing. 
• These cells do not have any logical functionality and only contains PG pins (i.e. no signal pins)
• example : Endcap/TAP/Filler/Decap cells, ESD/TCD cells

Special Cells:  

• There cells also not present in input Verilog netlist but serves unique purpose in physical design.
•  These cells may have logical functionality but are used for specific tasks.
• example :  Pad cells, Low-power cells (Levelshifters, Isolation cells, Retention cells, Power-switch cells), Tie(high/low) cells, Spare cells, 

Lets understand the significance of each cells.

Endcap/Boundary cells :

• Purpose : at the time of fabrication, these are changes of damage of gate of boundary cells. to prevent such damage,  Endcap/Boundary cells which  consist of dummy poly gate are added at boundary. so even if damage occurs, it can damage only dummy gate and protects the actual gate of stdcell.
• endcap cells should be placed where stdcell cell row are expected to be end. These cells are added at the end of site rows and around boundary of objects such as core area, Hard macros, Hard placement blockages, Corner cells, Voltage area.
• For advanced/lower technology nodes, appropriate selection of endcap cell reference is important as for each corners there are different endcap reference cells are required.
• Point to remember :   Left/right/top/bottom ,  inner : top-left/top-right/bottom-right/bottom-left , outer : top-left/top-right/bottom-right/bottom-left need to have different endcap reference.
• visually check weather appropriate endcap cell ref is user or not. ( most accurate method is FEOL drc)
• Endcap cells are placed after placing Macros/Hard blockages in Floorplan stage.
• EDA PNR tools have automated commands to create Endcap cells.
• as all Endcap cell reference are different for top/bottom/left/right/corners, all reference need to be mentioned in command.

TAP cells:

• Latch-up effect : in CMOS circuits, combination of p-type and n-type region created parasitic transistor and diodes which can form a thyristor like structure (p-n-p-n). this thyristor is generally inactive but triggers when there is sudden change in voltage at input or power supply or due to electrostatic discharge (ESD). once thyristor triggers, it enters to a conducting stage creating low resistance path between VDD-VSS can can damage the circuit.
• Purpose : to prevent above mentioned Latch-up effect, TAP cells are special purpose cells which contains N-well tie , P-substrate tie or both. TAP cells ensures the electrical integrity of chip.
• TAP cells are added at regular interval in stdcell site row and  maximum distance between two TAP cells defined in Foundry guideline.  TAP  distance can very across different Technology.
• Generally, TAP cells are placed after Endcap cells placement.
• EDA PNR tools have automated commands to create TAP cells.
• generally it requires max distance between two TAP cell coulmns.
• to reduce area, TAP cells are added in staggered manners(checker board pattern)  as shown in below :

• Guideline to ensure proper TAP cell placement :
• visually check if TAP cells are placed with required minimum distance.
• left/right edge of Hard macro, it would be better to have additional column of TAP cell to have robust tap cells placement (as inside macro, TAP distance might not be same from left/right boundary..!!!) [ refer above image ]
• 
  

FILLER Cells / Programable Filler cells :

• Purpose : during Chemical-Mechanical-Polishing(CMP), can cause the erosion and dishing. hence Filler cells help to have continuous N-Well or P-Well by balancing the density across chip. Filler cells contributes the mechanical stability of chip during manufacturing which reduce the chance of damage.
• Filler cells contains power(VDD) and ground(VSS) connectivity hence they maintain power-ground rail continuity across whole chip.
• Filler cells are added during Chip-finishing stage after all routing. 

• Programmable Filler cell : These are kind of Special cells  which normally acts as Filler cells only and based on requirement they can be act as spare cells by minor adjustment in pin connectivity.
• As these cells are already added in design during implementation stage, for any Functional eco can be achieved by without alteration in base layers.
• unlike Spare cells, these cells are filled in all empty region in placed of regular Filler cells.
• These cells helps to reduce turn-around time and its really cost effective as no need to change the base while using these cells.

WALL_CAP Cells:

• WALLCAP cells / Wall Decoupling capacitor cells are specialized physical only cells used in advanced lower Technology nodes.
• Purpose : These cells helps to provide decoupling capacitance which helps in power integritiy which reduces the noise in Power Delivery Network (PDN).
• Advanced nodes have stringent requirements of power delivery and density. WALLCAP cells helps to meets these requirements.
• These cells are placed along with Endcap/TAP cells. for uniformity, these cells are placed as a one column at regular intervals. 
• in Advance nodes, to meet complex rules, Endcap/Tap/WallCap cells are added together.

DECAP Cells:

• Decap cells are temporary capacitance added in design between power and ground rail which acts a  local reservoir of Charge which ensure that power supply remains stable during sudden change in current demand. 
• Voltage fluctuation can effect the delay/performance of logic cells which lead to IR drop and Timing challenges. Thus Decap cells  help in reducing IR drop and timing challenges.
• Decap cells are added in Chip-finishing stage prior to Filler cells.
• Internal structure:
• As Decap has act as a Capacitance and in CMOS, gate capacitance is dominant capacitance across all other capacitances, bellow is basic circuit of Decap from CMOS:

• In Design, most of power consumption is done by Clock network. as Clock cells are operating at high frequency and majority of clock cells are toggled at same time, there is possibility of high current drawn from power grid for small duration which leads to IR drop on given cells and eventually affecting the performance of cell.
• with presence of Decap cells, where there is drop in power grid, these cells act a battery and maintain the voltage level across the rail. 
• Synopsys ICC2 command for Filler/Decap insertion:
• create_stdcell_fillers -lib_cells <filler cells> -prefix fill

Spare Cells:

• Purpose : to all future enhancement in design by adding additional functionality, Spare cells are used without re-implicating the whole design.
• These cells are not connected to the functional logic of the design but are uniformly placed to allow for future modifications or engineering change orders (ECOs) without requiring a complete redesign of the chip.
• candidates for Spare cells : Generally universal gates such as NAND/NOR, FlipFlop , Mux , Buffer is used in one module of spare cells. each such modules are placed at uniform distance vertically/horizontally.
• EDA PNR tools have automated commands to add spare cells.
• it requires the ref name to be part of one spare cell module and minimum horizontal/vertical distance between two spare module.
• 
• Below is zoom version at one module:
• 
• Guideline to ensure proper Spare cell placement :
• visually check the placement of spare cells. each group of spare cells are placed uniform distance (vertical/horizontal) as expected. 

TIE Low/TIE High Cells:

• Definition: These are special-purpose cells used to provide constant logic values (0 or 1) to the inputs of other cells in a design.
• Purpose:
• TIE Low cells provide a constant logic 0.
• TIE High cells provide a constant logic 1.
• Significance: 
• Prevents floating inputs, which can cause unpredictable behavior or increased power consumption.
• Reduces the need for additional routing to connect inputs to power or ground.
• Usage: These cells are typically used for inputs of unused logic gates or for controlling specific design features

PAD cells:

• Definition: PAD cells are interface cells used to connect the internal logic of a chip to the external world through input/output (I/O) pins.
• Purpose:
• Provide electrical and mechanical connections between the chip and the package.
• Protect the internal circuitry from electrostatic discharge (ESD).
• Types:
• Input PADs: For receiving signals from external sources.
• Output PADs: For driving signals to external destinations.
• Bidirectional PADs: For signals that can act as both input and output.
• Power and Ground PADs: For supplying power and ground connections to the chip.
• Significance:
• Essential for chip functionality and reliability.
• Ensure proper signal integrity and ESD protection.

Level Shifter Cells:

• Definition: Level shifter cells are used to translate signal levels between different voltage domains in a design.
• Purpose:
• Ensure compatibility between blocks operating at different voltage levels.
• Prevent damage to low-voltage circuits when interfacing with high-voltage signals.
• Significance:
• Critical in designs with multiple power domains, such as low-power designs.
• Maintain signal integrity and prevent overvoltage or undervoltage issues.

Isolation Cells:

• Definition: Isolation cells are used to isolate power domains in a design, ensuring that signals do not propagate from a powered-off domain to an active domain.
• Purpose:
• Prevent leakage currents and undefined signal states when a power domain is turned off.
• Operation:
• When the source domain is powered off, the isolation cell outputs a predefined value (usually 0 or 1).
• Significance:
• Essential in power gating techniques for low-power designs.
• Prevents signal corruption and ensures proper operation of the active domains.

Retention Cells:

• Definition: Retention cells are special flip-flops or latches that retain their state even when the power to their domain is turned off.
• Purpose:
• Store critical state information during power-down modes.
• Allow the design to resume operation quickly without reinitializing the state.
• Significance:
• Widely used in low-power designs to save power while maintaining functionality.
• Enable efficient power management by allowing selective power-down of non-critical blocks.

In this post i have tried to cover majority used Physical/Special cells. 

If you have any queries or suggestions , Let me know in the comments. 

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