ASIC Physical Design : Key challenges and Innovative solutions

 Hi All, check below Challenge to revise your concepts related to Floorplan. Consider one FullChip with below specification: core-to-die : 1.014 Floorplan Shape : Rectangle Max routing layers : M15 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 M5 track offset : 0.026 Consider one block from FullChip from below specification: Block level ports in M5 layers (Horizontal direction) , M5 Pitch : 0.076 M5 track offset : 0.026 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 core-to-die : 1.014 Goal: Block-A and Block B is same. (instantiated two times in FullChip) in FullChip, Both blocks orientation is R0. In FullChip, two block (Block-A and Block-B) need to be placed as vertically stacked. ( i.e. 0 Y distance between two blocks) There shouldn't be FEOL/base drc violations and Ports of both blocks should be on track. Comment How to archive...

Hi All, check below Challenge to revise your concepts related to macro placement guidelines. Consider one block with below specification: core-to-die : 0 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 Consider below Macro: Macro pins in M5 layers in Horizontal layers , Pitch : 0.076 macro width : 10um Goal: Need to Place this macro in block without having FEOL drc and macro pins should be on track. Comment what should be macro origin i.e x,y location of lower left corner. Share your answer in comment.

 Hi All, Hope you have gone through the important aspect of  Floorplan i.e. "Macro Placement". if not, Please revies your concepts by clicking below link: Best Practices for Macro Placement Guideline in ASIC Physical Design Refer below image for Challenge: MEM1/MEM2/MEM3 are same Macro with same cell reference name.  distance between MEM1-->MEM2  is same as MEM2-->MEM3. in FEOL/base DRC, Latch-up issue is reported in between MEM2-->MEM3 while there is no Latch-up issue between MEM1-->MEM2. Please think and share your views what could be reason for Latch-up between MEM2-->MEM3.

 Hi All, to test your practical concepts related to Advanced STA, I have added more challenge. what will be slack of above Timing report. Comment your answer and share your views.

 Hi All, below case will test your practical concepts related to Floorplan. suppose, there is one design without any macros/IPs with Floorplan Aspect ratio as 1. site row height as 0.169 and site row width is 0.048. in all stdcells, applied keepout : left --> 0.24  ,  right --> 0.24 . left/right side core to die offset as 0.624 and top/bottom core to die offset is 1.014. for this design placeopt is completed (stdcells are legalized properly).   After completing placeopt, all Physical/Special cells are removed manually and also stdcell apart from instances with cell reference as INV8 are removed. (i.e. design is having only INV8 ref cells). stdcell utilization : 0.6 , Total stdcell area : 476.3772 , Total Core area : 793.962 From LEF, area of INV8  : 0.15412800 -------------------------------------------------------------------------------------------------------- What will be Total stdcell count ..? comment your answer below. To revise Floor...

 Hi ASIC Physical design enthusiasts, Suppose you received a Verilog netlist ( lets say temp.v ) and designer forgot to mention the top design/module name. There are multiple ways possible to get the top module name. Which approach you will use to find the design name ?  Please share the your approach with steps. If  scripting is required, mentioned the sequence of command/algorithms. Comment your views.

Hi All, Challenge to test your Floorplan concepts. what will be Core height and width as a output of  below command ?   initialize_floorplan  -boundary {{0 0}{10 10.01}} -core_offset "0.624 1.014 0.624 1.014" Please share  your views in comment. If you need help to revise concept, refer floorplan guide : Mastering Floorplanning: A Comprehensive Step-by-Step Guide"

 Hi All, Refer below image. all the dimensions are illustrated using ruler. What will be track_offset for given layer track showed in image? Type your answer in comment box. to get explanation : Floorplan Basics: Learn the Terms Without the Complexity

Below is Timing report for Advanced STA.  What will be setup slack in below path : Post your answer of Exact slack in comment box with justification.