ASIC Physical Design : Key challenges and Innovative solutions

 Hi All, Hope you have gone through Synthesis and Formal Verification posts. to test your knowledge, Check below challenge : In Synthesis, incase of sequential optimizations such as Register retiming and Multibit Register Banking, it can alter the structure between reference design and implemented design. this will cause Compare points mismatch  between reference design and implemented design. What would be Formality/Logic equivalence Check result ? PASS or FAIL ?

 Formal Verification is often referred as "The Heartbeat" of ASIC Physical design. Just as human body, despite having all body parts intact, it cannot function without heartbeat same way   If ASIC design PASSES w.r.t Timing/Physical verification/EMIR checks but Formal verification(Formality) is FAILED , Design is failed to perform as expected ...!!! Hence it is really important to have Formal verification checked at each stages of ASIC Physical design. As Synthesis is the first stage where RTL is converted to synthesized gate-level netlist, it becomes imperative to validate formal verification immediately after   synthesis to ensure design correctness and functionality. When one design is transformed/optimized, there are some cases when transformed design may not give same functionality as original design due to human errors, improper handling of EDA tool settings, bugs in EDA tools. Functional verification v/s Formal verification Functional verification and For...

 In Previous post, I have explained the importance of Logical synthesis. If you have not explored it, Please click below link to check it: Synthesis : The Soul of Physical Design In this post, Lets understand Practical significance of Physical synthesis. will understand each aspects of physical synthesis in comparison with Physical synthesis. Physical aware Synthesis As Synthesis(logic Synthesis) is Soul of Physical design and bridges gap between RTL and Physical implementation, Physical Synthesis bridges gap between Logical Synthesis and physical implementation.  Regular Physical Synthesis Flow: This is two step process. first logical synthesis is performed and using this synthesized netlist, Floorplan and macro/port placement is done. after Power-plan, DEF file is generated which contains Floorplan information and Macro/port placement along with PG grid. along with DEF file, other physical inputs are provided for Physical synthesis. output of Physical synthesis is synthesize...