Challenge 10 : Formality

 Hi All,


Hope you have gone through Synthesis and Formal Verification posts.

to test your knowledge, Check below challenge :


In Synthesis, incase of sequential optimizations such as Register retiming and Multibit Register Banking, it can alter the structure between reference design and implemented design. this will cause Compare points mismatch  between reference design and implemented design.

What would be Formality/Logic equivalence Check result ? PASS or FAIL ?

Comments

  1. AnonymousSeptember 8, 2025 at 6:02 PM

    It will pass the design because the modified information will storing in .svf or guidance file it will helps to pass the LEC and it will check only logical Equivalence whether it is getting same output with the same input or not ? so LEC will pass even when the modifications done

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    Replies
    1. JigneshSeptember 8, 2025 at 6:15 PM

      Thank you for sharing your views.
      Yes. You are totally right. But tool generated svd , formality should be fine.
      Could you please explain how to make formality/LEC PASS by using manual commands instead of svf files ?

      Delete
    2. JigneshSeptember 8, 2025 at 6:15 PM

      Thank you for sharing your views.
      Yes. You are totally right. But tool generated svd , formality should be fine.
      Could you please explain how to make formality/LEC PASS by using manual commands instead of svf files ?

      Delete

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