Floorplan stage : Key Inputs and Prerequisites

So far  previous blog pages explain the brief about ASIC Physical design flow. For quick glance of ASIC design flow, refer :  ASIC Design Flow . Now Lets deep dive into each steps of Physical design starting with "Floorplan inputs and Prerequisites".

Floorplan is the most important step in physical design implementation. it is like planning the layout of house before building it. Faulty floorplan leads to multiple challenges at subsequent stages of physical design flow such as placement, cts, routing...A good floorplan with proper Floorplan inputs sets the foundation for subsequent stages and significantly impacting the overall quality of results.

Floorplan stage : Key inputs 

The input for  floorplan stage are like the materials and plans you need before building a house. Below are key inputs of Floorplan :

1. Design information : 
• This refers to detailed gate level netlist representation of design containing the connectivity information of all elements including design ports, standard cells and macros. Generally Verilog netlist is available in .v format.
2. Design Library information :  
• It is the details about the stdcell/macros. The  list of stdcell and macros in the library  is superset of those present in the netlist.
• Design information is categorized  in two types :  Logical and Physical. 
• Physical Library : it describe the physical attributes of cells such as their size, shape and the physical location of pins. A common example of physical library is  Library exchange format (LEF), which is available in .lef format.
• Logical library : Defines  the logical attributes of cells such as functionality,  all input/output pin direction , timing information. A widely used example of timing library format is  .lib.
• EDA tools requires Logical/Physical library in specific format. for example, Synopsys ICC2/Fusion compiler uses New Design Model(NDM) which integrates both .lib and .lef data while  Cadence Innovous requires libraries in  .lib and .lef  format.
3. Technology information : 
• This file contains specific information about Technology i/e manufacturing process like layer details and spacing rules.  technology file is available in TECHLEF or .tf files
4. Floorplan information : 
• This refers to physical layout of design including shape(rectangle/rectilinear) and size(Height/width) of floorplan and physical placement of input/output ports.
• in larger SOCs ,  initial floorplan information for block is typically provided by fullchip team during top-won approach. This can later be refined based on block's design details using bottom-up approach.
5. Voltage areas/Power Intent - UPF(unified power format) : 
• only applicable to design uses multiple voltage
• contains information about different power domains

In the automation flow, several critical inputs are consolidated during the floorplan stage  to ensure smooth progression  in subsequent stages. Below are key inputs:

• Design constraints : 
•  these are the essential  rules for timing, power, area which design must need to meet. They are critical for placement and later stages. The most commonly used format for  specifying these constraints  is Synopsys Design Constraints(SDC) file typically provided in .sdc format.
• Multi Mode Multi Corner (MMMC) information:
• for advanced  technology nodes , Timing signoff involves multiple Process,  Voltage and Temperature (PVT) configurations.  to address this complexity, the multi mode multi corner approach is  used in Place-and-Route (PNR) tools across the scenarios.  This is also critical input for placement and subsequent stages.

You may also like : Floorplan in ASIC design flow

Floorplan stage : Prerequisites 

Before starting the floorplan stage, it s crucial to perform required sanity check for smooth design process.  The following perquisites should be validated:

• Quality of design check :
• Check the completeness and correctness of netlist. there are few command in EDA tools which can  provide all such information of design.
• multiple modules with same name: 
• each modules should be defined only on time in netlist. 
• undriven input pins : 
• Ensure there are no undriven and multi-driven pin as these can  lead to functional and timing issues in later stages. Undriven nets cause the unexpected value(X) propagation  through input pin which leads to affect the functionality.

• in above example, net2 is undriven net. (net2 is not logically connected to any driver)
• this case, output of cell D is not always guaranteed. for example, due to crosstalk impact between net1 and net2, its possible that D2 input might be 0/1/X. also if voltage value in between 0 and 1, cell D might not work as expected.
• unloaded output ports : 
• output ports without any connection referred as unloaded output. when such output ports are connected to other block's input ports, it can lead to unexpected value propagation.  If unloaded output ports are expected, it should be tie-off using tie-low/tie-high.

• in above image, out1/out2 are output ports of block1. out1 is floating/unloaded output port. 
• if block1 is connected to block2, its possible that cell A in block2 is underived. unwanted level can be propagated in input of cell A which lead to the functionality of cells A.
• out2 ports is connected to TIE0 cells. so there will b always 0 at input of cell B. so no issue.
• multi-driven nets : 
• multi-driven net connection happens when more than 1 driver is connected to any net/wire. in below image, output of cell A and B goes to input of cell C. here,  input net of cell C is considered as multi-driven. 

                                

• for signal nets, having multiple output values is not expected as if there are two different output value, it can create conflict. from above snap, if output of cell A is 1 and output of cell B is 0, there is conflict at input of cell C.
• for clock nets, its possible that clock is diverged from one point and then it converge at other point. this should be fine as "always" there will be same value in different output.

• in above case, output of CK0 cell is going to CK3  cell via cell CK1/CK2. input net of cell CK3 is multi driven. as there will always be same output (either 1 or 0) for CK1 and CK2, this multi driven net should be fine.
• pin direction mis-match : 
• ensure that each pins are having required direction from one of input/output/inout. 
• Formality : 
• make sure Formal verification is PASS against Original RTL and Synthesized gate-level netlist.
• Floorplan validation :
• It is essential to ensure that all necessary floorplan information is accurate and complete.   block's size(height-width) , shape (rectilinear or rectangle ) is must  need information before starting floorplan.
• Ensure  that physical location of all input/output ports are available otherwise it can impact the floorplan .
• Quality of library :
• Confirm that all cells  used in netlist are present in library. missing any cell information  leads to unresolved reference and can't be proceed  for further stage.
• All cells should be present in logical and physical library. cells having only timing or physical information affect the optimization and implementation.
• Quality of constraints :
• Validate SDC file to ensure it is syntactically correct and free of errors.
• Note that detailed constraints validation is broader topic and will be covered in an upcoming blog post.
• Power Intent and UPF validation :
• Validate UPF file to ensure that power domain, supply nets and voltage area are correctly defined and it needs to align with design's low power requirement

By addressing above perquisites , floorplan stage can proceed with confidence and reducing risk of issues in further stages. 

If you have any query/doubt related to Floorplan inputs/prerequisites, Please add in comments. i will try to resolve it.