ASIC Physical Design : Key challenges and Innovative solutions

 Hi All, below case will test your practical concepts related to Floorplan. suppose, there is one design without any macros/IPs with Floorplan Aspect ratio as 1. site row height as 0.169 and site row width is 0.048. in all stdcells, applied keepout : left --> 0.24  ,  right --> 0.24 . left/right side core to die offset as 0.624 and top/bottom core to die offset is 1.014. for this design placeopt is completed (stdcells are legalized properly).   After completing placeopt, all Physical/Special cells are removed manually and also stdcell apart from instances with cell reference as INV8 are removed. (i.e. design is having only INV8 ref cells). stdcell utilization : 0.6 , Total stdcell area : 476.3772 , Total Core area : 793.962 From LEF, area of INV8  : 0.15412800 -------------------------------------------------------------------------------------------------------- What will be Total stdcell count ..? comment your answer below. To revise Floor...

 Hi ASIC Physical design enthusiasts, Suppose you received a Verilog netlist ( lets say temp.v ) and designer forgot to mention the top design/module name. There are multiple ways possible to get the top module name. Which approach you will use to find the design name ?  Please share the your approach with steps. If  scripting is required, mentioned the sequence of command/algorithms. Comment your views.

Hi All, Challenge to test your Floorplan concepts. what will be Core height and width as a output of  below command ?   initialize_floorplan  -boundary {{0 0}{10 10.01}} -core_offset "0.624 1.014 0.624 1.014" Please share  your views in comment. If you need help to revise concept, refer floorplan guide : Mastering Floorplanning: A Comprehensive Step-by-Step Guide"

In the intricate world of Physical Design, placement and routing blockages often emerge as critical challenges as it can significantly impact the  quality of the design flow. These blockages, whether intentional or unintentional, play a pivotal role in defining the physical layout of a chip, influencing everything from timing closure to power distribution. Understanding how to effectively manage and strategize around these blockages is essential for achieving optimal design outcomes. In this blog, we will explore practical strategies and best practices to navigate placement and routing blockages, ensuring a smoother and more efficient design process while maintaining the integrity of the final product. Placement blockages Placement blockages are specific locations where placement of stdcell is restricted.  Placement Blockages are not guide to tool but it doesn't allow  PNR tools to place stdcell in given area.  By carefully managing placement blockages, designers can...

 Hi All, Refer below image. all the dimensions are illustrated using ruler. What will be track_offset for given layer track showed in image? Type your answer in comment box. to get explanation : Floorplan Basics: Learn the Terms Without the Complexity

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Floorplan is art of Physical design as mostly referred as  critical stage as quality of chip depends on how good is floorplan. If proper care is taken while doing floorplan, critical issues of subsequent stages can be reduced such as timing/congestion/EMIR/PDV related issues. Lets try to understand step by step process involved during Floorplan. 1. Die area estimation For larger SOCs, FullChip die area is decided in two stages:(below steps are iterative process until PPA is meet for chip. Top-down approach :  Initial die area is estimated based on hierarchy or sub-blocks of whole design. Once initial required area is identified, sub blocks are placed as per hierarchy grouping based on high level dataflow of design architecture. Once all sub-blocks are placed properly  within estimated die area...

In previous blog post, all necessary checks before starting floorplan was explained. It is very important to understand the significance of all Floorplan term before actually starting floorplan implementation. Lets deep dive into the floorplan basic terminologies in simple words. Here are the Floorplan terms and its significance. Full-Chip: The complete design of ASIC consists of  multiple blocks, Macro, standard cell (stdcell) ,IO PAD etc. This represents the final design which will be fabricated.  Block: It is smaller portion of FullChip design typically represent a sub module of Fullchip RTL code. Die-area:  This is total Physical area of Chip including core area and surrounding.  Die area determines the overall size of Chip and iMacs he manufacturing costs. larger die area increases the manufacturing cost. This is important factor for deciding overall PPA(power, performance, area) for any chip. Die-area may be not be in multiple of site row height but it must nee...

Below is Timing report for Advanced STA.  What will be setup slack in below path : Post your answer of Exact slack in comment box with justification. 

So far  previous blog pages explain the brief about ASIC Physical design flow. For quick glance of ASIC design flow, refer :  ASIC Design Flow . Now Lets deep dive into each steps of Physical design starting with "Floorplan inputs and Prerequisites". Floorplan is the most important step in physical design implementation. it is like planning the layout of house before building it. Faulty floorplan leads to multiple challenges at subsequent stages of physical design flow such as placement, cts, routing...A good floorplan with proper Floorplan inputs sets the foundation for subsequent stages and significantly impacting the overall quality of results. Floorplan stage : Key inputs  The input for  floorplan stage are like the materials and plans you need before building a house. Below are key inputs of Floorplan : Design information :  This refers to detailed gate level netlist representation of design containing the connectivity information of all elements...

 Hi All, Floorplanning is a critical step in the design and implementation of modern integrated circuits, serving as the foundation for achieving optimal performance, power, and area. This guide, " Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights ", is designed to demystify the complexities of floorplanning by seamlessly integrating theoretical concepts with real-world applications. I am creating separate pages for detail explanation of each topics related to Floorplan. If you are starting your Physical Design Journey, I would suggest to go through each post by clicking in specific order mentioned as below. Floorplan stage : Key Inputs and Prerequisites Floorplan Basics: Learn the Terms Without the Complexity Mastering Floorplanning: A Comprehensive Step-by-Step Guide Placement and Routing Blockages: Strategies for Optimal Design Flow Best Practices for Macro Placement Guideline in ASIC Physical Design Physical and Spare Cells: Foundations...