ASIC Physical Design : Key challenges and Innovative solutions

 Hi All, Refer below image. all the dimensions are illustrated using ruler. What will be track_offset for given layer track showed in image? Type your answer in comment box. to get explanation : Floorplan Basics: Learn the Terms Without the Complexity

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Floorplan is art of Physical design as mostly referred as  critical stage as quality of chip depends on how good is floorplan. If proper care is taken while doing floorplan, critical issues of subsequent stages can be reduced such as timing/congestion/EMIR/PDV related issues. Lets try to understand step by step process involved during Floorplan. 1. Die area estimation For larger SOCs, FullChip die area is decided in two stages:(below steps are iterative process until PPA is meet for chip. Top-down approach :  Initial die area is estimated based on hierarchy or sub-blocks of whole design. Once initial required area is identified, sub blocks are placed as per hierarchy grouping based on high level dataflow of design architecture. Once all sub-blocks are placed properly  within estimated die area...

In previous blog post, all necessary checks before starting floorplan was explained. It is very important to understand the significance of all Floorplan term before actually starting floorplan implementation. Lets deep dive into the floorplan basic terminologies in simple words. Here are the Floorplan terms and its significance. Full-Chip: The complete design of ASIC consists of  multiple blocks, Macro, standard cell (stdcell) ,IO PAD etc. This represents the final design which will be fabricated.  Block: It is smaller portion of FullChip design typically represent a sub module of Fullchip RTL code. Die-area:  This is total Physical area of Chip including core area and surrounding.  Die area determines the overall size of Chip and iMacs he manufacturing costs. larger die area increases the manufacturing cost. This is important factor for deciding overall PPA(power, performance, area) for any chip. Die-area may be not be in multiple of site row height but it must nee...

Below is Timing report for Advanced STA.  What will be setup slack in below path : Post your answer of Exact slack in comment box with justification. 

So far  previous blog pages explain the brief about ASIC Physical design flow. For quick glance of ASIC design flow, refer :  ASIC Design Flow . Now Lets deep dive into each steps of Physical design starting with "Floorplan inputs and Prerequisites". Floorplan is the most important step in physical design implementation. it is like planning the layout of house before building it. Faulty floorplan leads to multiple challenges at subsequent stages of physical design flow such as placement, cts, routing...A good floorplan with proper Floorplan inputs sets the foundation for subsequent stages and significantly impacting the overall quality of results. Floorplan stage : Key inputs  The input for  floorplan stage are like the materials and plans you need before building a house. Below are key inputs of Floorplan : Design information :  This refers to detailed gate level netlist representation of design containing the connectivity information of all elements...

 Hi All, Floorplanning is a critical step in the design and implementation of modern integrated circuits, serving as the foundation for achieving optimal performance, power, and area. This guide, " Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights ", is designed to demystify the complexities of floorplanning by seamlessly integrating theoretical concepts with real-world applications. I am creating separate pages for detail explanation of each topics related to Floorplan. If you are starting your Physical Design Journey, I would suggest to go through each post by clicking in specific order mentioned as below. Floorplan stage : Key Inputs and Prerequisites Floorplan Basics: Learn the Terms Without the Complexity Mastering Floorplanning: A Comprehensive Step-by-Step Guide Placement and Routing Blockages: Strategies for Optimal Design Flow Best Practices for Macro Placement Guideline in ASIC Physical Design Physical and Spare Cells: Foundations...

 Hi All, In the previous blog pages, we have extensively discussed the introduction of the ASIC design flow.( Please go through previous pages if not visited earlier) Each step in the flow holds its own unique significance and plays a critical role in the overall process.  But have you ever paused to consider the importance of the sequence of these stages ? Why is the order of these steps so crucial? in this blog, I delve into the reasoning behind specific ordering of the stages in ASIC design flow. 1. "DFT" :  why it is imperative to perform DFT only after Synthesis stage ..? why can't it be executed  earlier, i.e. right after RTL implementation ? Ans.  DFT is step to add  test logic  by implementing scan chain between two flops. at RTL level,  design is still high level abstract form and specific gate to flop interactions are not yet defined.  Synthesis translates RTL into gate-level netlist which provides necessary details for DFT insertio...

   Hi All, In previous blog, basic definition of all steps of " ASIC design flow " is explained.  Please check below lines which illustrates the analogy between " ASIC design flow " and " Music industry ". ------------------------------------------------ Analogy Between ASIC(Application-specific integrated circuit ) Design Flow and the Music Industry ASIC World : Front-End and Back-End. Music World : Song -- lyrics writing (corelates with Front-End) and Singing a song (corelates with Back-end). 1.  Specification  :    ASIC World : its related to specs of design functionality. Music World : before writing any song, its important to understand the requirement. i.e. song expressing  happy/romantic/sad/dance mood 2. A rchitectural implementation  : ASIC World :   specifications are converted into an algorithm/code which meets the design requirements. Music World : According to song requirement, high level frame work is created us...

 Hi All, Here is basic and simple  understanding of ASIC( Application specific integrated circuit ) design flow. 1.  Specification : For any ASIC design, first and main important step is "specification" .  to give simple analogy, this is the main requirement/target of design. for example , to prepare any recipe, its important to know which recipe you are going to make and what is your expectation i.e. taste,..etc. for ASIC , specification  can be no. if inputs/outputs , speed, etc...  2. A rchitectural implementation : this is high level step to define your design. this is the step where initial specifications are converted into an algorithm/code which satisfy the specification. in digital system words, this is RTL(register transfer language) implementation .  3. RTL verification : this is step to validate the earlier written algorithm/RTL code. in layman language, this process confirms that actual output of given algorithm/RTL code with the origina...

Hello All,  I am creating this blog to help all Physical Design Enthusiasts to gain knowledge on physical design fundamental concepts. On this blog spot ,  i will post all technical topics/queries and its solution. stating with ASIC flow and followed by each steps of Physical design in detail. (I will not cover very basic detail which are available in Google). I will try to make more practical approach which will help  to corelate Theory and Practical concepts. To get early updates/notifications of Posts and Frequent technical capsules, please subscribe. For frequent challenging question, I have create one group in LinkedIn: Click here to join the group :   ASIC Physical Design Enthusiasts If you have any suggestion for topic , Please share in comment box. if you have any doubt/query related to any topic, add in comment and i will share my views.