Challenge 7 : Latch-up issue
Hi All,
Hope you have gone through the important aspect of Floorplan i.e. "Macro Placement". if not, Please revies your concepts by clicking below link:
Refer below image for Challenge:
- MEM1/MEM2/MEM3 are same Macro with same cell reference name.
- distance between MEM1-->MEM2 is same as MEM2-->MEM3.
in FEOL/base DRC, Latch-up issue is reported in between MEM2-->MEM3 while there is no Latch-up issue between MEM1-->MEM2.
Please think and share your views what could be reason for Latch-up between MEM2-->MEM3.
What i can think of is mem1 to left edge spacing is different from mem3 to right edge spacing , but well tap are inserted at regular intervals. So there might be the case that are no well taps present in mem2 and mem3 channel…
ReplyDeleteAssume, tap insertion are same in both channels. Now could you think what could be reason for latch up violations in only one channel?
DeleteWhats the answer for this?
ReplyDeleteAnil,
DeleteI can understand your eagerness to know the answer!
Let's give other members to guess the answer.
Meanwhile you can check other pages/challenges.
Haha yeah 🫡
ReplyDeleteCan you also capture issues related to synthesis?
ReplyDeleteSure Anil.
DeleteThank you for suggestion.
Actually I was planning to have placement after but synthesys is also important. Hence I'll cover it first
can we have the Answer to this?
ReplyDeleteLatch up issue between mem2 and mem3 means high current is flowing. There are two possibilities I can think of :
ReplyDelete1. Current drawn by mem3 pin is higher as compared to mem2/mem1 pin
2. Short interconnect or less RC between mem2-mem3 as compared to mem1-mem2
I am guessing due to IP internal power used higher metal layers or its has less resistance . If it is wrong please correct me
ReplyDeleteCould you please elaborate how power requirements affect the LUP requirement?
DeleteBtw all the Macros are with same reference only.
It could be this case. Usually endcap also contains tap inside which can cover some channel length.but still if its having lup, itmeans there need another column of TAP cell. Mostly when imserting tap, it inserts from bottom left to top in column by column way or something, and here unluckily that interval is kimd of just not fitting the channel. Its hard to say it in words, what I mean is if we highlight tap cells the column might be missing in that channel. so need to do a WA to insert in that channel
ReplyDeleteAssume tap cells count and pattern are same in both channel. Now could you please think about why only one channel is having violation?
DeleteMay be due to there is not TAP cells inside macro ?
ReplyDeleteOne reason could be that MEM3 is flipped while MEM1 is not. Flipping changes which wells and diffusions sit at the edge. One orientation might line up N-well to N-well (safe), while the flipped side puts N-well against P-well with active diffusions close by. Same spacing, but the latch-up path only exists in the second case.
ReplyDeleteThank you for sharing your perspective here..
DeleteEndcap cells are added inside macro as well at next level, Endcap cells are added around macro.
How internal well/diffusion inside macro relates to outside rail/diffusion?
(That is one purpose of Endcap to break the well. Right?)