Challenge 4 : finding top module name from netlist
Hi ASIC Physical design enthusiasts,
Suppose you received a Verilog netlist ( lets say temp.v ) and designer forgot to mention the top design/module name.
There are multiple ways possible to get the top module name.
Which approach you will use to find the design name ?
Please share the your approach with steps. If scripting is required, mentioned the sequence of command/algorithms.
Comment your views.
I faced the similar issue while setting the top_module name in Primetime. I exported the data from FC and wants to do timing analysis in PT and was confused for which one is exactly the top module between the two modules names. I tried hit & trial at that time because there was only two module names were in list.
ReplyDelete* I set first one module name as a top_module and linked which given me a lot of errors and warnings related to undefined references, missing ports. It made me clear that this is definitely not the real top_module.
* I set then another module as a top_module and after that linking also happened properly.
I just made double sure by looking into the RTL file by grepping correct module name from the above and found this module was not instantiated while the other wrong module name was instantiated.
Thank you for sharing your experience...
DeleteYes...you were lucky as only two module were there in netlist....
Netlist may have thousands of modules , in that case some strong approach is required..
Please think and share your thoughts what can be done if there are large number of modules in netlist.
We can have a list of all the modules and now check for the its instantiation. If the module is instantiated then it's not a top_module. Finally, we'll be end up with one module which is not instantiated and this is our top_module.
DeleteAgree with your concept.
DeleteLet's consider practical example:
From netlist, grepped module... 1000 modules found.
Now how do ensure that which one is not instantiated? Checking each module name one by one is not engineering solution.! How would you do that ?
I've not tried this out, but thinking that we can have one script which will be doing the job of checking each modules for its instantiation.
DeleteHi Shubham,
DeleteYes.. script is one of possible way.
Could you please try to mention sequence of commands to be followed to achieve the goal here .?
Thank you, Sir
DeleteI'm not at all good at scripting, but I'll try to put my thoughts here. You can correct me.
Assuming RTL files are already read and elaborated by the tool and all the module names are unique, then can follow below sequence of commands:
1. set rtl_list { ./*.v} # Storing all RTL files
2. set module_list [] #Creating a list to store modules
3. foreach files in rtl_list {
set fp [open $file r]
set content [read $fp]
close $fp # Triggering a loop to read the content of all RTL files
4. Searching for module definitions using regexp, and storing it in module_list.
5. Iterating each module name for its instantiation from module_list, but I don't know how we can do that.
5. If the instantiation is found, remove the elements from the list.
6. After sorting, it will end up with only element that is not instantiated, and this is the top module.
7. Printing the top_module name
Sorry for the incomplete commands.
Thank you for your efforts Shubham.
DeleteI liked your approach. You need help for topic #5, but otherwise it was good approach.
i open the netlist and search for module from the last of the file, generally that module is the top level module.
ReplyDeleteI agree... If you are lucky enough, last module will be top module.. but this is not the always case (as a Physical design engineer, we should be ready for all worst conditions..!)
DeleteCould you please explain how to find?
ReplyDeleteI would go with below approach:
ReplyDelete1. Load all libs and read verilog netlist. This will give summary at end.
2. Without any tool:
Netlist : abc.v
grep "^module" abc.v | awk '{print $2}' > modules
Run for each loop on above list of "module" file and search if its count is exactly 1.
If it is 1, that mean that module is not called anywhere and that is top module.