Challenge 13 : Area optimization
****** Area Optimization ******
Suppose you have been given one design and respective Technology related files and been asked to Optimize area as much as possible considering reasonable Routing DRC numbers and reasonable Hold/Setup violations (Only Internal).
Data Provided:
- RTL
- Technology related data
You are allowed to modify below:
- Constraints : Constraints file is not given. you can use any constraints requires (but dont make all paths as False paths 🙂 ...!!!)
- Floorplan shape and size : any shape and size can be used
- Port Placement : no port placement is given. you can place ports in any layers, any location (no ports should be unplaced..!)
- any Synthesis/PnR implementation Tool can be used.
Goal:
- Overall area (stdcell/Physical cells) should be as minimum as possible
- Internal Setup/Hold timing should be less than uncertainty
- Routing DRC should be reasonable
There are many ways possible here. Please share your approach here.
Expecting Out of the Box approach.
Add your answer in comment box.
#VLSI #PhysicalDesign #Challenge #Optimization #PnR
Area optimization can be achieved using several methodologies. The first approach I prefer is using multibit cells, followed by logic restructuring. As a last option, we can consider flattening the entire design; however, this carries a risk, as the DFT logic may also get flattened, which is not recommended.
ReplyDeleteHi Bala,
DeleteNote that there are no constraints available.
Which constraints you will use here ..?
What we can do is we will implement the (N-1) design, and then for that (N-1) design, we will do porting so that the area will get reduced in the Nth design. Basically, the process of port punching can be implemented here. Please correct me if I am wrong
ReplyDeletePlease elaborate how will you do N-1 design?
DeleteWhat do you mean by port punching in this context.
Do we have macros?? Because it will effect our port and placement. Also constraints maynot be there but do we have frequency based on it we can write the basic constraints at partition level
ReplyDeleteNo macros in design.
DeleteYou can use any frequency you want.
End goal is to have as minimum area as possible along with other conditions given in problem statement
Here are the few methods which we can incorporate to have minimum area possible.
ReplyDelete1. Rectangle or square shape is recommended to mentain symmetry.
2. No or minimum number of CGCs.
3. Using only HVT cells in design. This will limit the high drive strebgth cells. Also variation across all signoff corner will be less.
4. Use only top two layers for Power Network and stacked vio till std cells power pins. This will help to get more routing resources and limit the use of buffer/inv.
5. Htree for clock distribution to minimize the skew and cbuf/cinv count.
Thank you for sharing your views.
DeletePlease clarify regarding #3.
How HVT helps to save area?
By mistake I typed HVT. Design should be implemented with LVT cells. LVT cells will be faster with good drivability which will help to reduce high drive strength cells.
DeleteCool !
DeleteThat makes sense!
Below are the few methods we can try
ReplyDelete1. During synth will enable the complex gated like HA FA, 4 I/P std cells to use less area and enabling MBIT cells
2. In DC we can enable the logic optimization by considering areas as high priority
3 if we have memories in the design we can give feedback to designer for selecting the memories by considering the area rather than power
4. Creating the square share core area initially and trimming the area wherever it is not used for STD cells to make as rectilinear
5. As the clock frequency not mentioned I will assume it is as min, will use MSCTS for better skew and and timing
6. Will enable higher VT cells and avoid upsizing
Hi Srinivas,
DeleteThank you for details here.
Yes. All above this can help to reduce overall area.
Please elaborate the purpose of High vt cells here.