Placement stage : Introduction

 Hi All,

I hope so far you have gone through all steps of ASIC Design flow before placement stages and ready to deep dive into placement. In this post, I will give basic introduction about placement optimization.

Before starting Placement stage, Below are the assumptions: 

• Floorplan size is reasonable with adequate initial utilization numbers
• all IO ports are placed as expected  and marked as Fixed
• all Placement blockages from FullChip (based on top-down approach) perspective is already there in floorplan 
• Macros are placed and marked as Fixed
• Design is Single power domain
• Power-Grid pre routed

Introduction to Placement stage

• In ASIC Physical design flow, goal of Placement is to place the standard cells(stdcell) in Core area which is further divided into stdcell rows.
• each standard cell must be placed on legal site rows such that it meets Timing and efficient routing. Thus "Placement" stage is key factor in ASIC Design Flow for achieving better PPA by optimizing area, routing congestion and Timing/DRV requirements.
• Placement algorithms are varies from one EDA PNR  tool to other EDA PNR tool however main end goal is same for all  tools.
• Efficient placement help to reduce manual fixes of Timing/DRCs during ECOs.

Inputs and output of Placement stage

• Below are the inputs of Placement stage :
• database with Floorplan and Powerplan. (should have all ports placed and marked Fixed , All Macros/IPs placement and marked Fix, required PG grid with reasonable PG DRCs)
• MCMM/Design Constraints files and RC tables/TluPlus files ( if already provided before floorplan, it would be saved in database. in that case, no need to provide again)
• UPF files (only for multi-voltage designs)
• scan-def ( for scan chain reordering) : by default input netlist contains the scan connectivity but  it is required to achieve minimum wire length by scan chain re-ordering.
• Below are outputs of Placement stage:
• Optimized database w.r.t PPA (Power, Performance, Area) with standard cell placed on legal location
• required reports (Timing/Area/DRV/Utilization/Congestion/... reports)

Key steps in Placement flow

• Placement flow in EDA mainly takes two steps : Coarse placement and Detail placement/optimization.
• Coarse placement : 
• This is initial step in placement which involves placement of all cells in Core area  based on netlist connectivity. 
• main objective is place stdcell close to each other in each module of design.
• Below is steps involved in Coarse placement :
• Tie high/low cells additional based on 1'b0 or 1'b1 from Synthesized netlist
• Wirelength optimization
• Scan chain Optimization (re-ordering to achieve minimal wire-length)
• Cell spreading ad clustering depending density of design
• Initial Timing optimization
• Initial Congestion optimization 
• Power optimization
• Design netlist generated using Logical Synthesis might not accurate buffer/inverter additional  due to wire-load model, generally EDA PNR tools removes all buffers/inverters from logical synthesized netlist and re-inserts based on design constraints such as maximum transition, maximum capacitance, maximum fanout.
• In this steps, stdcell overlaps possible as stdcells are not legalized yet.
• previously defined Placement blockages are honored by this step.
• Detail placement/Optimization:
• After coarse placement, Fine placement optimizes design w.r.t Timing, Area, Congestion and Power by using various optimization techniques.
• main objective is to meet Design setup requirement  with minimum Congestion and Power consumption and Design rule constraints( DRVs).
• Detail placement also make sure that cells are placed at legalized location. Thus, it is really important to check if there is any issue during legalization.

Legalization :

• to understand how legalizer engine is working, it is really important to understand few key terminologies. 
• Site row : site rows are different for each Technology nodes.  site row height and site row width is defined in Technology LEF file.
• site row orientation : site row orientation is created along with Floorplan size creation.  each site rows can have either R0/MY or MX/R180 orientation.
• Cell orientation : EDA PNR tool specificizes the Cell orientation.  Orientation can be further categorized as 1. Based on Flipping/mirroring w.r.t axis 2. Based on rotation 
• Below are type of Cell Orientation based on Flipping. 

• R0 - Base orientation
• MY - Mirror w.r.t Y axis
• MX - Mirror w.r.t. X axis
• R180 - Mirror of MY orientation w.r.t X axis
• Below are type of Cell Orientation based on Flipping. 

• from R0 , other orientations are derived by Rotating cell in clock-wise direction.
• for Legalization, Site row orientation and cell orientation must be same.
• Placement Spacing label : Often placement spacing are defined on  cells having more pins to avoid pin density and congestion issues.
• For example, consider that on cell A , 1X spacing is applied and on cell B 2X spacing applied only on left side.
• From below image, A and C are valid while B and C are invalid placement.

• Lib cells having low pass rate for legalization should be marked as Dont use.

Please let me know if any query on basic placement understanding. you can write in comment box for any topics related to placement. i will try to cover it in upcoming posts.

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