Why Order Matters: Understanding the Sequence of ASIC Design Stages

 Hi All,

In the previous blog pages, we have extensively discussed the introduction of the ASIC design flow.( Please go through previous pages if not visited earlier) Each step in the flow holds its own unique significance and plays a critical role in the overall process.  But have you ever paused to consider the importance of the sequence of these stages ? Why is the order of these steps so crucial? in this blog, I delve into the reasoning behind specific ordering of the stages in ASIC design flow.

1. "DFT" :  why it is imperative to perform DFT only after Synthesis stage ..? why can't it be executed  earlier, i.e. right after RTL implementation ?

Ans. 

• DFT is step to add  test logic  by implementing scan chain between two flops. at RTL level,  design is still high level abstract form and specific gate to flop interactions are not yet defined.  Synthesis translates RTL into gate-level netlist which provides necessary details for DFT insertion.
• EDA tools are designed to work with gate-level netlist and without gate-level netlist, these tools can't perform effectively.

2. "Floorplan" : can Floorplan be performed prior to Synthesis ? 

Ans.

• If you follow typical orthodox ASIC design flow, your answer would be "no"  but answer  is partially correct. Answer to this question is "yes - it can be". 
• in typical ASIC flow , Floorplan is performed as per this sequence : Synthesis --> DFT --> Floorplan. However in modern ASIC design implementation, few EDA(Electronic Design Automation) tools provide the feature to perform Physical aware synthesis/DFT insertion with physical floorplan information. This approach helps in Complex ASIC chips where timing/congestion are challenging due to floorplan side.

3. "Powerplan" : can Powerplan be performed prior to Floorplan ? 

Ans.

• Generally, powerplan is performed after floorplan however power plan can be performed before floorplan stage.
• initial power plan, such as high level Power-Ground(PG) grid creation, defining voltage areas, can be done before detailed floorplaning to ensure robustness of  PG grid. however this requires PG grid modification such as PG cutting over Hard Macros based on placement of Hard Macros.
• In lower technology nodes, physical cells such as endcap cells, TAP cells are typically added before the powerplan step. This is because these cells are essential for proper physical and electrical integrity of design and their placement can influence the PG grid. in few cased, these cells can be added or minor adjustment can be done after powerplan.

 

4. "Placement" : can Placement be performed before powerplanning ?

Ans.

• as per standard practice, Placement must needs to be performed after powerplan (This is the recommendation..!!). However placement before powerplan is used in specific scenarios and it is not standard practice. 
• The standard physical design flow involves completing powerplan before detailed placement to ensure the robustness of PG grid. However there are few scenarios where placement is performed before powerplan but it is referred as "Preliminary/early" placement.  
• Placement of stdcell can affect lower layer  PG grid specially in  density regions or  design with multiple power domains.

5. "Clock tree synthesis - CTS" : can CTS be performed before placement ?

Ans.

• No. CTS can't be performed prior to Placement stage.
• as detailed CTS  needs placement information of sequential elements such as Flops,Latches,Macros without detailed placement tool does not have necessary information about distribution of clocked elements hence it is impossible to build detailed CTS before placement.
• in some advanced design methodology such as Multi-sourced clock tree synthesis (MSCTS) some portion of CTS can be done prior to placement.

6. "Routing": can Routing  be performed before CTS ?

Ans.

• No. as CTS is critical component  of design and it significantly impacts the Routing resources and timing.

7. "Signoff" : can signoff be performed before/during PNR ?

Ans.

• There is no obvious answer to this question. 
• As Physical design implementation is iterative process, "Signoff" stage acts as a feedback process to overall quality of design.  Hence it is important that majority of signoff checks can be checked in PNR stage itself.

This is all about importance/understanding the sequence of ASIC design stages. 

Please share your feedbacks and let me know if any query/doubt related to this topic. I will try to answer.