Challenge 14 : Advanced STA
Hi All,
Challenge on Advanced STA.
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Macro Placement Guidelines in ASIC Physical Design
clock domain is different for FF1 and FF2, Asynchronous
ReplyDeleteClock source of CLK1 and CLK2 is same. Hence both clock are synchronous.
DeleteWhether CLK1 and CLK2 are synchronous or asynchronous to each other?
ReplyDeleteBoth clocks are synchronous.
DeleteNeed to set logically exclusive clock group for
ReplyDeleteClocks reaching mux
ReplyDeleteOkay. So you will define clock exclusive between CLK1 and CLK2 ?
DeleteDefine gen clocks at output of mux then apply logically exclusive clock groups, or physical exclusive depending on your crosstalk need to Performed or not
DeleteDefine generated clock at output of mux wrt master clocks.
ReplyDeletePut generated clock as physically exclusive.
There would be some clock gating checks which needs to define for mux if sel line is not constant?
Hi Anil,
DeleteIs it possible to generate two clock on same pin ?
Yes , it can be defined… -add option and also -master
DeleteYes .. correct
DeleteIn order to define two generated clocks on same pin, need to have additional settings or proper command.
ReplyDeleteI believe you are following.
We can follow two approaches.
ReplyDelete1.Define generated clocks on mux output and keep them logical exclusive.
2. Keep clock mux exclusivity on mux output.
Hi Mukund,
DeleteCould you please explain why logical exclusive needs to be applied.
-add
ReplyDeleteSo since multiple clock is reaching to a single mux, timing check in FF3 4 will be in 4 cases. start/end with clk1, start/end with clk2, start/end with clk1/2 and vice versa. But since mux will select from clk 1/2 timing paths in tart/end with clk1/2 and vice versa shouldnt be seen. Need constr on this.
ReplyDeleteI guess the way we give constraint will also impact CTS quality.
Yes..
DeleteProper constraints helps to build high quality CTS.
there are two ways to constraint at the mux
ReplyDeletecase 1 : create generated clocks at input pins of the mux w.r.t master clock and set the constraint "set_clock_groups -physically_exclusive -group CLK1 -group CLK2"
case 2: set the app option "timing_enable_auto_mux_clock_exclusivity " to true. which enables auto inference of clock muxes.
correct me if im wrong
Srinadh,
DeleteCould you please elaborate why physical exclusive used here?
sorry thats my bad... its logically_exclusive
Delete