Setup Slack Optimization techniques at Placeopt stage

 When it comes to timing optimization techniques, there are many techniques present but it depend on the stage in ASIC Physical Design flow. fixing methods and timing recipes are different at different stage. generally timing methods should be applied based on the stage i.e. one fixing method might be valies for timing fix but it can't be applied to all the stages.

Timing Fixing techniques at Placeopt stage

• Timing fixing methods at the Placeopt stage can be broadly categorized into two main approaches:
• Automatic Tool-Based Techniques: all  EDA tools  can perform automated optimizations, such as buffer insertion, cell resizing, and high fanout net (HFN) optimization, which helps in timing optimization.
• Manual Timing Fixing Methods: These involves user -driven adjustments on top of the EDA default optimization.
• Lets discuss both techniques in detail.

Automatic Tool-Based Techniques:

• Buffer insertion :  
• generally inserting buffer on long net helps to reduce overall datapath which helps in setup violations.
• at placeopt stage, EDA tools automatically added buffers based on requirement such as bad transition , large capacitance. 
• This method can't be consider as user based method to fix setup violation ( during Signoff stage, definitely manual buffer insertion in one of method to fix timing.!)
• instead of manually adding buffer, need to analyze why EDA tool is not able to add buffer . by approaching in this direction, it might helps to identify root case such as  more cell density , congestion , dont touch on net etc...
• Cell Resizing(upsizing/downsizing) :
• yes. you read it right,! sometime cell downsizing also helps to fix setup violation.!
• if cell delay is more due to large load, by upsizing the drive cell helps to reduce cells delay ( cell delay depends on input transition and output load.!)
• if two cells are placed very close to each other  and load cell(cells2) is high drive strength cell , by downsizing the load cell helps to reduce driver cell(cells1) delay as  output load is reduced. ( provided load load is not driving much further distance.! refer below image)

• generally this is automatically done by EDA tool during placement optimization.
• HFNS (High Fanout Synthesis):
• in case of high fanout nets, drive cell has the more delay.
• EDA tool automatically does High Fanout Synthesis by properly adding required buffer tree reducing overall fanout count for driver cell.
• to control this behavior more effectively, optimization constraints such as max_fanout constrains can be applied. some time this can also be used to guide placement engine by setting required  EDA tool application option.
• Cloning / Load Splitting :
• if any cell is driving hugh fanout, EDA tool splits the fanout by duplicating drive cell.
• Cloning automatically done by EDA tool if any data path cell has more fanout.
• VT swap:
• In timing critical path,  EDA tool can automatically use lover VT cells to reduce cell delay.
• sometime to control the lower VT cell count, VT percentage is applied. 
• during signoff stage, VT swap can be done manually but placement stage practically manual VT swap should be avoided.
• if tool is not able to use lower VT, need to check if VT percentage threshold is reach or cell is marked as dont_touch.
• Timing Driven Placement:
• EDA tool optimize the cell placement by relocating cells at required location.
• for example if one flop is having multiple fanout, EDA tool tries the place the flop near to its fanout cone logic.
• more timing critical cells are placed closure to reduce overall wire-length.
• Logic Restructuring
• EDA tool can optimize the boolean equation to optimize the datapath in critical path.
• example :
• Z = (AB) + (AC)
• In this case, tool might need two AND gate and 1 OR gate.  if there is any timing path through these cells (2 AND and 1 OR gate), tool might optimize boolean equation as below :
• Z' = A (B+C)
• This requires only two cells which might helps in overall PPA.
• Combination Merging/de-merging  is automatically done by EDA tool based on requirement.
• This can't be done manually during signoff fixes as it can lead to  routing changes/DRC.
• Pin Swapping
• for cells having more than 1 pins, if any pin arc delay is more and that pin is part of critical timing path, EDA tools can internally swap the pins.
• pin swapping cant affect the functionality but it helps to reduce timing violations. 
• example :
• Z = AB
• lets assume A pin is connected to low drive strength cell and B pin connected to high drive strength cells. there is critical timing path through A pin.
• EDA tool can swap A and B pin connection i.e. A pin connection with high drive strength cell.
• In signoff, it is difficult to do pin swapping as it requires addition analysis and it may lead to  routing changes/DRC.

Manual Timing Fixing Methods:

• Path Group:
• If there is unique Startpoint/Endpopint pattern is violating leading to more contribution in TNS, creating path group is efficient method.
• applying weightage  on given path group, EDA tool gives more priority to fix these paths over other paths.
• Bound/Region/Fence Creation
• during placement stage, EDA tool tries to place same hierarchy cells closure. if there is any timing path from one group of hierarchy to other croups of hierarchy,  its possible that respective startpoint/endpoint cells can be placed far and might leads to timing violations.
• to restrict the placement of certain group of cells in given area, Bound/Region/Fence is used
• by creating proper bound, overall distance can be reduces which helps to reduce timing violations.
• bound creation requires more detailed analysis as it requires proper analysis upstream and downstream like how those  paths  looks visually  and what is positive slack margin available.
• Magnet Placement 
• Magnet Placement is a technique used to guide the placement of cells by creating "magnetic" regions that attract specific cells or groups of cells. 
• This is often used to optimize timing or reduce congestion by clustering related cells together.
• Magnet placement required one fixed object around which other objects can be magnetized. 
• for example, pin of any fixed Macro , IO ports
• Intentionally introduce skew to make path more pessimistic
• in placement stage, as clock is idle default skew is 0ps ( unless CCD- Concurrent Clock and data optimization  is not turned on in placement stage.!)
• if any path need more focus from EDA tool, intentionally skew can be added by below approaches :
• apply +ve launch clock latency
• apply -ve capture clock latency
• This make oaths more pessimistic and tool can focus more to optimize datapath.
• generally this technique is used to fix reg2clockgate path as these paths will have -ve skew in CTS stage leading to more violation in CTS.
• Relative placement 
• if there is soft memory logic where the requirement is to have all flops placed very close in proper sequence  (like row and column) , relative placement is really helpful to control the cell placement. 

Hope you liked the explanation...

Please let me know if any other scenario you observed during placement optimization... will try to cover that as well.