STA : Timing path types

 In STA, timing analysis done from one point to other point which is referred as timing path.

before understanding timing, lets understand the basic terminology :

Startpoint

• In STA terminology, startpoint refers to the point from where data is launched. 
• There are two types of valid startpoint
• Input data port
• For any block, first data transmit occur from input data port
• note that clock port can't be considered as startpoint as there is no data signal launching from clock port.
• clock pin of any sequential cell
• there are mainly  three types of sequential cells : flops , latches and hard macros
• as data is launched at active edge of clock ( for flops and macro)  and active level of clock (for latch) , clock pin is considered as startpoint
• note that output pin of any sequential cell (such as Q pin of flop ) is not considered as startpoint 

Endpoint

• In STA terminology, endpoint refers to the point  where data is captured.
• There are two types of valid endpoint
• Output data port
• For any block, data can be captured as output port
• input data pin of any sequential cell
• as data is captured  at input data pin of any sequential cell , input data pin can be considered as endpoint

Timing path 

• Timing path always starts from startpoint and ends at endpoint.
• startpoint is refers as launch point and endpoint is refers to capture point.
• if max delay constraints is applied, it  creates artificial startpoint and endpoint ..!! 
• for example, mad delay is applied from one pin of combo cell (Cell1/A) to next combo cell pin (Cell2/B) , cell1/A  act as startpoint and cell2/B act as  endpoint.
• any idea which will happen if you apply max delay constraints from any data pin of sequential cell ..?
• As there are two types of valid startpoint and two types of valid endpoint , total 4 combinations possible hence timing paths are mainly divided on 4 types listed below.
• In2reg
• reg2reg
• reg2out
• in2out

Lets try to understand each category in detail .

1. In2reg 

• Timing path starting from input port and ending at input data pin of any sequential is in2reg path.
• in2reg paths requires "Input external delay" as  this is only one half of full timing path ( at fullchip level, it can be actual reg2reg path).  
• Input delay is used in percentage of clock period.
• for example, for 1000ps clock period, 60% input delay = 60% of 1000ps = 600ps
• mean it is assumed that 600ps is already consumed outside the block and   only 400ps is allowed in given block
• in2reg paths are critical as it will affect timing at fullchip level. eventhough block level  internal timing is clean but there is in2reg violations, it can lead to timing violation at fullchip level.
• if lunch flop ( in other block of fullchip) operates at difference frequency compared to capture flop, input delay is specified using virtual clock. [ assuming both clocks are synchronous .! ] 
• as there is input port on the launch side, there is no launch clock latency , this make setup optimistic as there is always positive skew at block level. but at fullchip level there will be always some skew. to remove this optimism , virtual latency is applied on virtual clock ( assuming clocks are balanced properly at fullchip , generally average value of all capture flops is applied as virtual clock latency. 

2. reg2reg 

• These category is considered as pure internal timing path within given block level.
• as there is launch and capture cell in block itself, in this type of timing path, actual launch and capture delay comes into picture and hence clock skew plays as important role here. 
• reg2reg can be further divided into below category :
• flop2flop / reg2reg path
• this is pure flop to flop path.
• flop2latch / flop2ckgt
• this is one of critical and challenging  timing path among all the paths.
• generally, these category of paths has more launch latency and less capture latency hence it is bit challenging even though datapath is properly optimized.  
• mem2reg / mem2flop
• as generally macro in bigger in size, this paths becomes critical if there is more macro access time (macro internal delay )
• reg2mem / flop2mem
• if macro has very stringent setup and hold requirement,  this paths may become setup and hold critical if not optimized properly in earlier stages.

3. reg2out 

• Timing path starting from clock pin of any sequential cell and ending at output data port is  referred in2reg path.
• reg2out paths requires "Output external delay" as  this is only one half of full timing path ( at fullchip level, it can be actual reg2reg path).  
• Output delay is defined as  percentage of clock period.
• for example, for 1000ps clock period, 60% output delay = 60% of 1000ps = 600ps
• mean it is assumed that 600ps is already consumed outside the block and   only 400ps is allowed in given block
• reg2out paths are critical as it will affect timing as fullchip level. eventhough block level  internal timing is clean but there is reg2out violations, it can lead to timing violation at fullchip level.
• as there is output port on the capture side, there is no launch clock latency , this make setup pessimistic  as there is always negative skew at block level. but at fullchip level there will be always some skew. to remove this pessimism, virtual latency is applied on virtual clock ( assuming clocks are balanced properly at fullchip , generally average value of all capture flops is applied as virtual clock latency. 

4. in2out 

• These paths also referred as Feedthrough paths
• if there is launch and capture clock are different compared to given block , sometime max delay constraints are also applied to optimized datapath as much as possible.

apart from above main category,  sometime there are multi cycle , half cycle paths , false path possible depending on timing exception or clock connectivity.

Please let me know if any other timing path category you come across.