ASIC Physical Design : Key challenges and Innovative solutions

 ASIC Physical Design consists of various stages. each with its own critical importance and significance. quality of each stage directly impacts the subsequent stages, Hence it is really important to ensure the high quality execution of initial stages to achieve efficient  and effective physical design implementation. In this post, will discuss detail significance about "Synthesis". Synthesis : The Soul of Physical Design Synthesis can be considered as "The Soul" of Physical Design. Synthesis serves as critical bridge between high level design abstract(RTL) and Physical design implementation. Below are few points makes Synthesis as "Heart" of Physical design. Translation of RTL into technology depended gate-level netlist :  as ASIC is Technology depended (90nm,65nm,28nm...) and RTL(register transfer logic) is technology independent , Synthesis is the first stage where RTL is converted to technology depended.  Optimization : During Synthesis, Design is opt...

 Hi All, check below Challenge to revise your concepts related to Floorplan. Consider one FullChip with below specification: core-to-die : 1.014 Floorplan Shape : Rectangle Max routing layers : M15 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 M5 track offset : 0.026 Consider one block from FullChip from below specification: Block level ports in M5 layers (Horizontal direction) , M5 Pitch : 0.076 M5 track offset : 0.026 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 core-to-die : 1.014 Goal: Block-A and Block B is same. (instantiated two times in FullChip) in FullChip, Both blocks orientation is R0. In FullChip, two block (Block-A and Block-B) need to be placed as vertically stacked. ( i.e. 0 Y distance between two blocks) There shouldn't be FEOL/base drc violations and Ports of both blocks should be on track. Comment How to archive...

Hi All, check below Challenge to revise your concepts related to macro placement guidelines. Consider one block with below specification: core-to-die : 0 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 Consider below Macro: Macro pins in M5 layers in Horizontal layers , Pitch : 0.076 macro width : 10um Goal: Need to Place this macro in block without having FEOL drc and macro pins should be on track. Comment what should be macro origin i.e x,y location of lower left corner. Share your answer in comment.