ASIC Physical Design : Key challenges and Innovative solutions

 Hi All, check below Challenge to revise your concepts related to Floorplan. Consider one FullChip with below specification: core-to-die : 1.014 Floorplan Shape : Rectangle Max routing layers : M15 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 M5 track offset : 0.026 Consider one block from FullChip from below specification: Block level ports in M5 layers (Horizontal direction) , M5 Pitch : 0.076 M5 track offset : 0.026 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 core-to-die : 1.014 Goal: Block-A and Block B is same. (instantiated two times in FullChip) in FullChip, Both blocks orientation is R0. In FullChip, two block (Block-A and Block-B) need to be placed as vertically stacked. ( i.e. 0 Y distance between two blocks) There shouldn't be FEOL/base drc violations and Ports of both blocks should be on track. Comment How to archive...

Hi All, check below Challenge to revise your concepts related to macro placement guidelines. Consider one block with below specification: core-to-die : 0 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 Consider below Macro: Macro pins in M5 layers in Horizontal layers , Pitch : 0.076 macro width : 10um Goal: Need to Place this macro in block without having FEOL drc and macro pins should be on track. Comment what should be macro origin i.e x,y location of lower left corner. Share your answer in comment.

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Before going to placement and further stages, its is really important that readiness of floorplan is verified which will help to reduce upcoming stage issues in subsequent stage for Physical design.. Generally all checked are done during individual steps of Floorplan, but is it also recommended to go through all checks before moving to further stages. This is 7th topics from " Mastering Floorplan " series. If you are directly reading  this post from blog, I would suggest to go through below main post which helps to understand the sequence of different floorplan topic: Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights Cell row/Total Utilization Ensure reasonable Cells row/Total Utilization is used. aggressive utilization (>90%) can lead to unavoidable issues in lat...