ASIC Physical Design : Key challenges and Innovative solutions

 ASIC Physical Design consists of various stages. each with its own critical importance and significance. quality of each stage directly impacts the subsequent stages, Hence it is really important to ensure the high quality execution of initial stages to achieve efficient  and effective physical design implementation. In this post, will discuss detail significance about "Synthesis". Synthesis : The Soul of Physical Design Synthesis can be considered as "The Soul" of Physical Design. Synthesis serves as critical bridge between high level design abstract(RTL) and Physical design implementation. Below are few points makes Synthesis as "Heart" of Physical design. Translation of RTL into technology depended gate-level netlist :  as ASIC is Technology depended (90nm,65nm,28nm...) and RTL(register transfer logic) is technology independent , Synthesis is the first stage where RTL is converted to technology depended.  Optimization : During Synthesis, Design is opt...

 Hi All, check below Challenge to revise your concepts related to Floorplan. Consider one FullChip with below specification: core-to-die : 1.014 Floorplan Shape : Rectangle Max routing layers : M15 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 M5 track offset : 0.026 Consider one block from FullChip from below specification: Block level ports in M5 layers (Horizontal direction) , M5 Pitch : 0.076 M5 track offset : 0.026 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 core-to-die : 1.014 Goal: Block-A and Block B is same. (instantiated two times in FullChip) in FullChip, Both blocks orientation is R0. In FullChip, two block (Block-A and Block-B) need to be placed as vertically stacked. ( i.e. 0 Y distance between two blocks) There shouldn't be FEOL/base drc violations and Ports of both blocks should be on track. Comment How to archive...

Hi All, check below Challenge to revise your concepts related to macro placement guidelines. Consider one block with below specification: core-to-die : 0 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 Consider below Macro: Macro pins in M5 layers in Horizontal layers , Pitch : 0.076 macro width : 10um Goal: Need to Place this macro in block without having FEOL drc and macro pins should be on track. Comment what should be macro origin i.e x,y location of lower left corner. Share your answer in comment.

 As per regular ASIC flow, Floorplan stage is referred as first stage of Physical Design (for advanced node considering Physical Synthesis, Physical Synthesis is first ...!!!). Before going to placement and further stages, its is really important that readiness of floorplan is verified which will help to reduce upcoming stage issues in subsequent stage for Physical design.. Generally all checked are done during individual steps of Floorplan, but is it also recommended to go through all checks before moving to further stages. This is 7th topics from " Mastering Floorplan " series. If you are directly reading  this post from blog, I would suggest to go through below main post which helps to understand the sequence of different floorplan topic: Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights Cell row/Total Utilization Ensure reasonable Cells row/Total Utilization is used. aggressive utilization (>90%) can lead to unavoidable issues in lat...

 In all Previous blog ports, step by step process of Floorplan till macro placement is explained. Now lets discuss the importance of "Physical/Special cells" in ASIC Physical Design. This is 6th topics from " Mastering Floorplan " series. If you are directly reading  this post from blog, I would suggest to go through below main post which helps to understand the sequence of different floorplan topic: Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights Physical/Special cell :     These cells which  are different then regular logical gates and  serves unique purpose in Physical Design. These cells don't contribute in logical function but its crucial  to have them in design for physical integrity and manufacturability of chip. Physical Cells :   These  are not present in input Verilog netlist are referred as Physical only cells.  These cells are generally not appeared  in Timing report and typically us...

 Hi All, Hope you have gone through the important aspect of  Floorplan i.e. "Macro Placement". if not, Please revies your concepts by clicking below link: Best Practices for Macro Placement Guideline in ASIC Physical Design Refer below image for Challenge: MEM1/MEM2/MEM3 are same Macro with same cell reference name.  distance between MEM1-->MEM2  is same as MEM2-->MEM3. in FEOL/base DRC, Latch-up issue is reported in between MEM2-->MEM3 while there is no Latch-up issue between MEM1-->MEM2. Please think and share your views what could be reason for Latch-up between MEM2-->MEM3.

 Hi All, to test your practical concepts related to Advanced STA, I have added more challenge. what will be slack of above Timing report. Comment your answer and share your views.

In all Previous blogs, Floorplan terminology and requirement before starting floorplan is explained. in this article, Lets  discuss the macro placement guideline. Macro placement satisfying the set of rules will ease the physical design and reduced the challenges at subsequent stages of Physical Design flow. Generally Macros are bigger in size, which cause critical design issues leading to increase wire net delay , cross-talk , IR drop. Hence these guidelines are help to save lots of time in future stages of flow. This is 5th topics from " Mastering Floorplan " series. If you are reading directly this post from blog, I would suggest to go through this blog which helps to understand the sequence of different floorplan topic: Mastering Floorplanning: A Comprehensive Guide Bridging Theory and Practical Insights Before starting macro-placement, Below are the assumptions:  Floorplan size is reasonable with adequate initial utilization numbers all IO ports are placed as expected...

 Hi All, below case will test your practical concepts related to Floorplan. suppose, there is one design without any macros/IPs with Floorplan Aspect ratio as 1. site row height as 0.169 and site row width is 0.048. in all stdcells, applied keepout : left --> 0.24  ,  right --> 0.24 . left/right side core to die offset as 0.624 and top/bottom core to die offset is 1.014. for this design placeopt is completed (stdcells are legalized properly).   After completing placeopt, all Physical/Special cells are removed manually and also stdcell apart from instances with cell reference as INV8 are removed. (i.e. design is having only INV8 ref cells). stdcell utilization : 0.6 , Total stdcell area : 476.3772 , Total Core area : 793.962 From LEF, area of INV8  : 0.15412800 -------------------------------------------------------------------------------------------------------- What will be Total stdcell count ..? comment your answer below. To revise Floor...

 Hi ASIC Physical design enthusiasts, Suppose you received a Verilog netlist ( lets say temp.v ) and designer forgot to mention the top design/module name. There are multiple ways possible to get the top module name. Which approach you will use to find the design name ?  Please share the your approach with steps. If  scripting is required, mentioned the sequence of command/algorithms. Comment your views.