ASIC Physical Design : Key challenges and Innovative solutions

 Hi All, check below Challenge to revise your concepts related to Floorplan. Consider one FullChip with below specification: core-to-die : 1.014 Floorplan Shape : Rectangle Max routing layers : M15 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 M5 track offset : 0.026 Consider one block from FullChip from below specification: Block level ports in M5 layers (Horizontal direction) , M5 Pitch : 0.076 M5 track offset : 0.026 Floorplan Shape : Rectangle Max routing layers : M13 site row height : 0.169 site row width : 0.048 FinFET grid (Y) : 0.026 FinFET grid (X) : 0.0005 core-to-die : 1.014 Goal: Block-A and Block B is same. (instantiated two times in FullChip) in FullChip, Both blocks orientation is R0. In FullChip, two block (Block-A and Block-B) need to be placed as vertically stacked. ( i.e. 0 Y distance between two blocks) There shouldn't be FEOL/base drc violations and Ports of both blocks should be on track. Comment How to archive...

Below is Timing report for Advanced STA.  What will be setup slack in below path : Post your answer of Exact slack in comment box with justification. 

 Hi All, In the previous blog pages, we have extensively discussed the introduction of the ASIC design flow.( Please go through previous pages if not visited earlier) Each step in the flow holds its own unique significance and plays a critical role in the overall process.  But have you ever paused to consider the importance of the sequence of these stages ? Why is the order of these steps so crucial? in this blog, I delve into the reasoning behind specific ordering of the stages in ASIC design flow. 1. "DFT" :  why it is imperative to perform DFT only after Synthesis stage ..? why can't it be executed  earlier, i.e. right after RTL implementation ? Ans.  DFT is step to add  test logic  by implementing scan chain between two flops. at RTL level,  design is still high level abstract form and specific gate to flop interactions are not yet defined.  Synthesis translates RTL into gate-level netlist which provides necessary details for DFT insertio...

 Hi All, Here is basic and simple  understanding of ASIC( Application specific integrated circuit ) design flow. 1.  Specification : For any ASIC design, first and main important step is "specification" .  to give simple analogy, this is the main requirement/target of design. for example , to prepare any recipe, its important to know which recipe you are going to make and what is your expectation i.e. taste,..etc. for ASIC , specification  can be no. if inputs/outputs , speed, etc...  2. A rchitectural implementation : this is high level step to define your design. this is the step where initial specifications are converted into an algorithm/code which satisfy the specification. in digital system words, this is RTL(register transfer language) implementation .  3. RTL verification : this is step to validate the earlier written algorithm/RTL code. in layman language, this process confirms that actual output of given algorithm/RTL code with the origina...