ASIC Physical Design : Key challenges and Innovative solutions

****** Area Optimization ****** Suppose you have been given one design and respective Technology related files and been asked to Optimize area as much as possible considering reasonable Routing DRC numbers and reasonable Hold/Setup violations (Only Internal). Data Provided: - RTL - Technology related data You are allowed to modify below: - Constraints : Constraints file is not given. you can use any constraints requires (but dont make all paths as False paths 🙂 ...!!!) - Floorplan shape and size : any shape and size can be used - Port Placement : no port placement is given. you can place ports in any layers, any location (no ports should be unplaced..!) - any Synthesis/PnR implementation Tool can be used. Goal: - Overall area ( stdcell / Physical cells ) should be as minimum as possible - Internal Setup/Hold timing should be less than uncertainty - Routing DRC should be reasonable There are many ways possible here. Please share your approach here. Expecting Out of the B...

  **** ASIC Physical Design ECO Challenge**** Assume below scenario: Design is clean w.r.t Timing Qor/Physical Verification/EMIR. -- Base layer is Frozen. [ good for Tapout ] Timing is Clean Signoff Physical Verification is Clean EMIR is Clean Formality is PASS Due to some Functional ECO, design is opened again and new timing violations were observed. Attempted Timing violations through metal-layers optimization only. after optimization, Timing is Clean Signoff DRC is Clean Signoff ERC/LVS is clean EMIR is Clean Formality is PASS Base layer XoR is clean w.r.t before ECO Is this good to Tapout this design ? Share your answer as "Yes" or "No" in comment box. I will share my views later as first would like to give opportunities to all members to share their views.