ASIC Physical Design : Key challenges and Innovative solutions

 Hi All, Hope you have gone through posts related to Flooroplan and Synthesis. Lets understand importance of PowerPlan in ASIC design flow. PowerPlan In older Technology nodes, main priorities were given to Timing and Area because these parameters  were dominant over power . however in lower nodes, as devices are shrinking there are more numbers of devices in same area. Also to supply power to these smaller devices, Power supply also becoming smaller over a time ( consider mobile batteries. its size keep reducing in last 10 years..!!! and also supply power is also reduced i.e. in older nodes, supply voltage in range of 1.5-2 V while it is drastically reducing now a days within 0.6-0.8 range).  in lower nodes, to address complex timing challenges power consumption is increasing   hence in  power is more dominant over area and timing.  Terminologies Power PAD : it is source from where chip get the power from external world. for wire-bounding Technology,...

****** Area Optimization ****** Suppose you have been given one design and respective Technology  related files and been asked to Optimize area as much as possible considering reasonable Routing DRC numbers and reasonable Hold/Setup violations   (Only Internal). Data Provided: - RTL  - Technology related data You are allowed to modify below: - Constraints :  Constraints file is not given. you can use any constraints requires (but dont make all paths as False paths 🙂 ...!!!) - Floorplan shape and size : any shape and size can be used - Port Placement : no port placement is given. you can place ports in any layers, any location (no ports should be unplaced..!) - any Synthesis/PnR implementation Tool can be used. Goal: - Overall area (stdcell/Physical cells) should be as minimum as possible - Internal Setup/Hold timing should be less than uncertainty - Routing DRC should be reasonable  There are many ways possible here. Please share your approach here.  ...

  **** ASIC Physical Design ECO Challenge**** Assume below scenario: Design is clean w.r.t Timing Qor/Physical Verification/EMIR. -- Base layer is Frozen. [ good for Tapout ] Timing is Clean Signoff Physical Verification is Clean EMIR is Clean Formality is PASS Due to some Functional ECO, design is opened again and new timing violations were observed. Attempted Timing violations through metal-layers optimization only. after optimization, Timing is Clean Signoff DRC is Clean Signoff ERC/LVS is clean EMIR is Clean Formality is PASS Base layer XoR is clean w.r.t before ECO Is this good to Tapout this design ? Share your answer as "Yes" or "No" in comment box. I will share my views later as first would like to give opportunities to all members to share their views.

 Static Timing Analysis (STA) in chip design can be  correlated with the nervous system of the human body. Below are few analogies : Signal Propagation In STA, Signal propagation from one sequential element to other element is analyzed and it is make sure that it meet requirement such as Setup/Hold slack. Similarly, Nervous systems ensures that nerves signals propagate properly between brain, spinal cord and other body part. Critical paths in STA, it is really important to identify and critical paths same ways, in body it is important to analyze critical paths such as spinal cord and  Constraints In STA, Constraints plays import role for critical paths. The nervous system also has constraints, such as reaction times, which must be within limits for the body to respond effectively. Optimization: STA helps optimize the design to minimize timing violations by following constraints. The nervous system adapts and optimizes signal transmission, for example, by strengthening neu...