Introduction to ASIC- Physical Design
Hello All, I am creating this blog to help all physical design enthusiasts to gain knowledge on physical design. On this blog spot , i will post all technical queries and its solution.
For more information, please stay-tuned ..!!
In Cts stage given by high preference skew or latency and why
ReplyDeleteSkew and latency will b impacting on timing , so
ReplyDeletewell, it depends on the design.
ReplyDeleteinsertion delay :
design which required very less throughput , needs minimum insertion delay ( less insertion delay , mean in less time clock reaches to sink.. if insertion delay is more , i.e. more than clock period , those initial clock period cycle will require to initialize the design causing less input)
Skew:
in general , minimum skew is expected ( to meet Timing issues). but if there is very low skew (for example, less than 5ps) , it will cause all sinks to be toggle/active at same time , which leads to more power consumption. also to minimize the skew, it requires addition of extra clock buffer which leads "area" increase. that is why very big skew is not expected or not very less skew is expected.
Hope this clarifies your query.
What is min period, why it occurs, what will it affect, how to fix it from STA or PD
ReplyDeleteMin Period : This is signoff check to ensure quality of clock network. this is checked either low-low or high-high. if clock pulse is degraded due to cross-talk or other reasons, clock reaching to sink will not have same period as expected leading to improper functionality of sequential element.
DeleteHope this clarify your doubt.
1. What is Min pulse width violation, how to fix it? 2. Lets say if you get min pulse width violation even after replacing with clk buffers how will you fix it?
ReplyDeleteMin pulse width: This is signoff check to ensure quality of clock network. this is checked either low-high or high-low. if clock pulse is degraded due to cross-talk or other reasons, clock reaching to sink will not have same pulse as expected leading to improper functionality of sequential element.
DeleteFix:
check clock network... if there is any cross-talk or other issue such as derates will lead to min pulse width violations. ( explanation: x-talk --> applied +ve on launch and -ve on capture hence to will increase pulse width loss)
there is not just one way to fix min pulse width i.e. only replacing clock buffers..!
more will explain in separate blog.
Hope this clarify your doubt.
On which basis these tree structures are decided in the CTS stage?
ReplyDeleteThere are may factor need to consider while building CTS... pls watch this space for a more info on this... i will create separate page on that.
DeleteIs Isolation cells require in clock path? when clock crossing different switchable domains
ReplyDeleteWell..as per my view, isolation cells are must required to prevent undefined output(X) propogated to next cell.
DeleteYes , isolation cells use in clock path because clock path has more switching activity so, if any cell has undefined output we get metastability then functionality will change,to over come this we use isolation cells to define the value as either 0 or 1.
DeleteHow clock Tree will build in CTS stage and how to fix skew& latency, what is the use of clock Trunk.
ReplyDeleteWell, to answer your question, it needs seperate article.
DeleteI am planning to create one post on this topic as well.
Just to give idea, there are multiple things need to take into consideration while building cts.
Also different approaches are there to improve skew/latency.