A quick glance to ASIC design flow

 Hi All,


Here is basic and simple  understanding of ASIC(Application specific integrated circuit) design flow.


1. Specification : For any ASIC design, first and main important step is "specification" .  to give simple analogy, this is the main requirement/target of design. for example , to prepare any recipe, its important to know which recipe you are going to make and what is your expectation i.e. taste,..etc. for ASIC , specification  can be no. if inputs/outputs , speed, etc... 

2. Architectural implementation : this is high level step to define your design. this is the step where initial specifications are converted into an algorithm/code which satisfy the specification. in digital system words, this is RTL(register transfer language) implementation . 

3. RTL verification : this is step to validate the earlier written algorithm/RTL code. in layman language, this process confirms that actual output of given algorithm/RTL code with the original specifications. 

4. Synthesis : this step converts RTL code to technology specific design. ASIC design is implemented in various technology i.e. 28nm,16nm,7nm..etc.  RTL code is general for all technologies.  there are few specifications which deciding the technology. for example, design speed is once of aspect to look for preferable  technology needs to be selected. 

5. DFT (Design for testability) :  Fabricated ASIC chip contains all functionality is implemented into small silicon.  to validate this scan post production DFT is important step. during this step, small logic (not related to actual design specification) is added and this logic will helps post production  debug process.

6. Floorplan : this is first step where generally Physical design cycle starts. (In my initial days, i was also considering the same but this is older concepts though..!!). now a days for recent complex designs , Physical design plays important roles starting from RTL implementation. in Layman language, initial steps such as RTL coding/Synthesis/.. are developed considering impacts at later stages of physical design. Floorplan step decides the overall dimensions of ASIC chips which also includes the placement of IO ports as well as placing the main blocks/macros.

7. Power-Plan : this steps ensures that each elements of design i.e stdcell/macros/IP gets the required power. Power-plan contains Power-Ground Pads and respective Power-Ground straps/rings.

8. Placement : this is process of assigning placement of stdcells on chips by maintaining required criteria.  Timing and congestion is one of those criteria. 

 9.CTS ( Clock Tree Synthesis) : As design contains Synchronous elements such as flops/memories , this steps ensures that uniform clock distribution is done  from main clock source to all synchronous aliments such that all such aliments gets clock with minimum insertion delay/skew.

10. Routing : This steps involves the physical routing of all signal nets. 

11. Signoff : This is similar as checklist to ensure the quality of design. there are various process such as Timing closure , Physical Verification , EMIR etc.. this steps is been considered as last stage in ASIC design (with ~20% weightage) , but this is partial true only..!!! depending on quality of all processes such as timing,physical_verification , adequate feedbacks need to be provided to earlier step such that quality of results improves. ( otherwise for this 20% weightage task , it requires 80% of efforts during signoff  ..!!)


This is all about basic introduction of ASIC design flow. I have tried not to include complex terminologies such that its easier for everyone. (Actual definitions of all tasks might need more accurate terminologies ).


Please mention your feedbacks/suggestions and queries. I will try to answer.


I am having 12+ years of experience in ASIC physical design industry.

Comments

  1. Anonymous6 July 2025 at 06:44

    Cts stage lo high preference skew or latency ? And why justify your answer

    ReplyDelete
    Replies
    1. Anonymous6 July 2025 at 10:32

      Both are interlinked, if skew is high then latency is less .if latency is high means skew is less .

      Delete
    2. Jignesh6 July 2025 at 21:59

      Hi,
      this is not always the same case.... high skew doesn't always mean less latency and vice-versa.
      recipe to control skew/latency is different.

      Delete
    3. Jignesh6 July 2025 at 22:02

      Here is my view on this...
      well, it depends on the design.
      insertion delay :
      design which required very less throughput , needs minimum insertion delay ( less insertion delay , mean in less time clock reaches to sink.. if insertion delay is more , i.e. more than clock period , those initial clock period cycle will require to initialize the design causing less input)
      Skew:
      in general , minimum skew is expected ( to meet Timing issues). but if there is very low skew (for example, less than 5ps) , it will cause all sinks to be toggle/active at same time , which leads to more power consumption. also to minimize the skew, it requires addition of extra clock buffer which leads "area" increase. that is why very big skew is not expected or not very less skew is expected.
      Hope this clarifies your query.

      Delete

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