Why Order Matters: Understanding the Sequence of ASIC Design Stages
Hi All, In the previous blog pages, we have extensively discussed the introduction of the ASIC design flow.( Please go through previous pages if not visited earlier) Each step in the flow holds its own unique significance and plays a critical role in the overall process. But have you ever paused to consider the importance of the sequence of these stages ? Why is the order of these steps so crucial? in this blog, I delve into the reasoning behind specific ordering of the stages in ASIC design flow. 1. "DFT" : why it is imperative to perform DFT only after Synthesis stage ..? why can't it be executed earlier, i.e. right after RTL implementation ? Ans. DFT is step to add test logic by implementing scan chain between two flops. at RTL level, design is still high level abstract form and specific gate to flop interactions are not yet defined. Synthesis translates RTL into gate-level netlist which provides necessary details for DFT insertio...